FPGA implementation of high performance digital FIR filter design using a hybrid adder and multiplier
V Thamizharasan, N Kasthuri - International Journal of Electronics, 2023 - Taylor & Francis
The energetic growth in portable multimedia and mobile communication system has
increased the requirement of high-speed signal processing system with compact area and …
increased the requirement of high-speed signal processing system with compact area and …
High throughput and energy efficient linear phase FIR filter architectures
P Patali, ST Kassim - Microprocessors and Microsystems, 2021 - Elsevier
High throughput, low complex and energy efficient linear phase FIR filter structures with low
latency are highly desirable for most of the portable signal processing applications …
latency are highly desirable for most of the portable signal processing applications …
[HTML][HTML] Design of efficient binary multiplier architecture using hybrid compressor with FPGA implementation
V Thamizharasan, V Parthipan - Scientific Reports, 2024 - nature.com
In signal processing applications, the multipliers are essential component of arithmetic
functional units in many applications, like digital signal processors, image/video processing …
functional units in many applications, like digital signal processors, image/video processing …
Digital Filter Architecture Based on Modified Winograd Method F (2× 2, 5× 5) and Residue Number System
Improving the characteristics of digital signal processing devices is an important task in
many practical problems. The paper proposes the architecture of a two-dimensional digital …
many practical problems. The paper proposes the architecture of a two-dimensional digital …
Design of an improved low-power and high-speed booth multiplier
A Rafiq, SM Chaudhry - Circuits, Systems, and Signal Processing, 2021 - Springer
This paper presents an improved 8× 8-bit Booth multiplier with reduced power, delay and
area. The major operations that consume power and are responsible for larger critical path …
area. The major operations that consume power and are responsible for larger critical path …
ASIC implementation of ECG denoising FIR filter by using hybrid Vedic–Wallace tree multiplier
S Janwadkar, R Dhavse - International Journal of Circuit Theory …, 2024 - Wiley Online Library
The design of hand‐held portable devices for cardiovascular health monitoring based on the
analysis of electrocardiogram (ECG) is a hot topic of research nowadays. Digital filters …
analysis of electrocardiogram (ECG) is a hot topic of research nowadays. Digital filters …
Enhanced FPGA linear phase FIR filter with amalgam multiplier
Designing high-performance integrated circuits that balance area, speed, and power is
increasingly challenging. This study optimises hardware implementation of FIR filters using …
increasingly challenging. This study optimises hardware implementation of FIR filters using …
Low-Complexity Distributed Arithmetic-Based Architecture for Inner-Product of Variable Vectors
Distributed arithmetic (DA) is generally used for area-time efficient implementation of inner
products, where one of the vectors is fixed and known a priori. Therefore, the conventional …
products, where one of the vectors is fixed and known a priori. Therefore, the conventional …
Efficient Radix-4 Approximated Modified Booth Multiplier for Signal Processing and Computer Vision: A Probabilistic Design Approach
BG Gowda, HC Prashanth… - … on Quality Electronic …, 2024 - ieeexplore.ieee.org
Approximation in arithmetic computations is accepted widely in error-resilient image and
signal processing applications, in which the computation time is more critical than accuracy …
signal processing applications, in which the computation time is more critical than accuracy …
An efficient design for FIR filter transposed structure
B Gopi, K Umapathy, E Sivanantham… - AIP Conference …, 2023 - pubs.aip.org
The innovative filter is built utilizing a low-power VLSI technology and a filter design that
employs the shift and add multiplier. The new FIR is comparable to existing FIR models in …
employs the shift and add multiplier. The new FIR is comparable to existing FIR models in …