With the down-scaling of CMOS technology, the design complexity of very large-scale
integrated is increasing. Although the application of machine learning (ML) techniques in …

Due to the increasing size of integrated circuits (ICs), their design and optimization phases
(ie, computer-aided design, CAD) grow increasingly complex. At design time, a large design …

Boosting Algorithm (BA) is state-of-the-art in major competitions, especially in the M4 and
M5 time series forecasting competitions. However, the use of BA requires tedious feature …

Macro placement is a critical very large-scale integration (VLSI) physical design problem
that significantly impacts the design power-performance-area (PPA) metrics. This paper …

Hardware Description Language (HDL) is a common entry point for designing digital circuits.
Differences in HDL coding styles and design choices may lead to considerably different …

Physical design flow through associated electronic design automation (EDA) tools plays an
imperative role in the advanced integrated circuit design. Mostly, the parameters fed into …

Net length is a key proxy metric for optimizing timing and power across various stages of a
standard digital design flow. However, the bulk of net length information is not available until …

In today's RTL-to-GDS flow domain, there is a lack of standards for reporting of design and
tool metrics. Moreover, each tool or engine has its own set of parameters that can change …

In modern VLSI design flow, the register-transfer level (RTL) stage is a critical point, where
designers define precise design behavior with hardware description languages (HDLs) like …

Within the Electronic Design Automation (EDA) domain, AI-driven solutions have emerged
as formidable tools, yet they typically augment rather than redefine existing methodologies …