RTL to transistor level power modeling and estimation techniques for FPGA and ASIC: A survey
Power consumption constitutes a major challenge for electronics circuits. One possible way
to deal with this issue is to consider it very soon in the design process in order to explore …
to deal with this issue is to consider it very soon in the design process in order to explore …
An energy efficient FPGA partial reconfiguration based micro-architectural technique for IoT applications
Low power consumption and high computational performance are two important processor
design goals for IoT applications. Achieving both design goals in one processor architecture …
design goals for IoT applications. Achieving both design goals in one processor architecture …
HL-Pow: A learning-based power modeling framework for high-level synthesis
High-level synthesis (HLS) enables designers to customize hardware designs efficiently.
However, it is still challenging to foresee the correlation between power consumption and …
However, it is still challenging to foresee the correlation between power consumption and …
Powergear: Early-stage power estimation in FPGA HLS via heterogeneous edge-centric GNNs
Power estimation is the basis of many hardware optimization strategies. However, it is still
challenging to offer accurate power estimation at an early stage such as high-level synthesis …
challenging to offer accurate power estimation at an early stage such as high-level synthesis …
Hard-odt: Hardware-friendly online decision tree learning algorithm and system
Decision trees are machine learning models commonly used in various application
scenarios. In the era of big data, traditional decision tree induction algorithms are not …
scenarios. In the era of big data, traditional decision tree induction algorithms are not …
Hl-pow: learning-assisted pre-RTL power modeling and optimization for FPGA HLS
High-level synthesis (HLS) enables designers to customize hardware designs without the
need for delving into low-level hardware details. However, it is still challenging to establish …
need for delving into low-level hardware details. However, it is still challenging to establish …
Data-Pattern-Based Predictive On-Chip Power Meter in DNN Accelerator
Advanced power management techniques, such as voltage drop mitigation and fast power
management, can greatly enhance energy efficiency in contemporary hardware design …
management, can greatly enhance energy efficiency in contemporary hardware design …
Efficient runtime power modeling with on-chip power meters
Z Xie - Proceedings of the 2023 International Symposium on …, 2023 - dl.acm.org
Accurate and efficient power modeling techniques are crucial for both design-time power
optimization and runtime on-chip IC management. In prior research, different types of power …
optimization and runtime on-chip IC management. In prior research, different types of power …
Protection of six‐phase transmission line using recursive estimation of non‐linear autoregression model coefficients and decision tree
Ever‐increasing energy demands and limited right of way over land motivates the adoption
of six‐phase power transmission. However, the wider recognition of six‐phase transmission …
of six‐phase power transmission. However, the wider recognition of six‐phase transmission …
High-Level Online Power Monitoring of FPGA IP Based on Machine Learning
Nowadays, power optimization has become a major interest for most digital hardware
designers. Some, traditionally, might stick to offline power estimation especially in early …
designers. Some, traditionally, might stick to offline power estimation especially in early …