[图书][B] On-chip communication architectures: system on chip interconnect
S Pasricha, N Dutt - 2010 - books.google.com
Over the past decade, system-on-chip (SoC) designs have evolved to address the ever
increasing complexity of applications, fueled by the era of digital convergence …
increasing complexity of applications, fueled by the era of digital convergence …
[图书][B] Design of cost-efficient interconnect processing units: Spidergon STNoC
M Coppola, MD Grammatikakis, R Locatelli… - 2020 - taylorfrancis.com
Streamlined Design Solutions Specifically for NoCTo solve critical network-on-chip (NoC)
architecture and design problems related to structure, performance and modularity …
architecture and design problems related to structure, performance and modularity …
PowerViP: Soc power estimation framework at transaction level
In this work, we propose a SoC power estimation framework built on our system-level
simulation environment. Our framework provides designers with the system-level power …
simulation environment. Our framework provides designers with the system-level power …
A power estimation methodology for systemc transaction level models
Majority of existing works on system level power estimation have focused on the processor,
while there are very few that address power consumption of peripherals in a SoC. With the …
while there are very few that address power consumption of peripherals in a SoC. With the …
Power analysis of system-level on-chip communication architectures
K Lahiri, A Raghunathan - Proceedings of the 2nd IEEE/ACM/IFIP …, 2004 - dl.acm.org
For complex System-on-chips (SoCs) fabricated in nanometer technologies, the system-
level on-chip communication architecture is emerging as a significant source of power …
level on-chip communication architecture is emerging as a significant source of power …
Power estimation methodology for a high-level synthesis framework
S Ahuja, DA Mathaikutty, G Singh… - … on Quality Electronic …, 2009 - ieeexplore.ieee.org
As adoption of system-level hardware design is increasing in industry and academia,
accurate power estimation at this level is becoming important. In this paper, we present a …
accurate power estimation at this level is becoming important. In this paper, we present a …
Enabling accurate modeling of power and energy consumption in an ARM-based System-on-Chip
J Nunez-Yanez, G Lore - Microprocessors and Microsystems, 2013 - Elsevier
Motivated by the importance of energy consumption in mobile electronics this work
describes a methodology developed at ARM for power modeling and energy estimation in …
describes a methodology developed at ARM for power modeling and energy estimation in …
Modeling power consumption and temperature in TLM models
M Moy, C Helmstetter, T Bouhadiba… - Leibniz Transactions on …, 2016 - hal.science
Many techniques and tools exist to estimate the power consumption and the temperature
map of a chip. These tools help the hardware designers develop power efficient chips in the …
map of a chip. These tools help the hardware designers develop power efficient chips in the …
A new multi-channel on-chip-bus architecture for system-on-chips
S Lee, C Lee, HJ Lee - IEEE International SOC Conference …, 2004 - ieeexplore.ieee.org
We can integrate more IP blocks on the same silicon die as the development of fabrication
technologies and EDA tools. Consequently, we can design complicated SoC architecture …
technologies and EDA tools. Consequently, we can design complicated SoC architecture …
Addressing resource contention and timing predictability for multi-core architectures with shared memory interconnects
H Wang, NC Audsley, W Chang - 2020 IEEE Real-Time and …, 2020 - ieeexplore.ieee.org
Multi-core architectures are increasingly being used in real-time embedded systems. In
general, such systems have more processors than the shared memory modules, potentially …
general, such systems have more processors than the shared memory modules, potentially …