Design of robust, energy-efficient full adders for deep-submicrometer design using hybrid-CMOS logic style

S Goel, A Kumar, MA Bayoumi - IEEE Transactions on Very …, 2006 - ieeexplore.ieee.org
We present a new design for a 1-b full adder featuring hybrid-CMOS design style. The quest
to achieve a good-drivability, noise-robustness, and low-energy operations for deep …

Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates

HT Bui, Y Wang, Y Jiang - … on Circuits and Systems II: Analog …, 2002 - ieeexplore.ieee.org
Full adders are important components in applications such as digital signal processors
(DSP) architectures and microprocessors. In this paper, we propose a technique to build a …

A novel high-speed and energy efficient 10-transistor full adder design

JF Lin, YT Hwang, MH Sheu… - IEEE Transactions on …, 2007 - ieeexplore.ieee.org
In this paper, we propose a novel full adder design using as few as ten transistors per bit.
Compared with other low-gate-count full adder designs using pass transistor logic, the …

A novel multiplexer-based low-power full adder

Y Jiang, A Al-Sheraidah, Y Wang… - IEEE Transactions on …, 2004 - ieeexplore.ieee.org
The 1-bit full adder circuit is a very important component in the design of application specific
integrated circuits. This paper presents a novel low-power multiplexer-based 1-bit full adder …

Noise and process variation tolerant, low-power, high-speed, and low-energy full adders in CNFET technology

YS Mehrabani, M Eshghi - IEEE Transactions on Very Large …, 2016 - ieeexplore.ieee.org
In this paper, a number of novel 1-bit full adder cells using carbon nanotube field-effect
transistor devices are presented. First of all, some two-input XOR/XNOR circuits are …

Design and analysis of a novel low-power and energy-efficient 18T hybrid full adder

M Amini-Valashani, M Ayat, S Mirzakuchaki - Microelectronics journal, 2018 - Elsevier
A novel full-swing, low-power and energy-aware full adder using hybrid logic scheme is
presented in this paper. At first, a new energy-efficient 10T XOR-XNOR cell is designed by …

A novel low-power full-adder cell for low voltage

K Navi, M Maeen, V Foroutan, S Timarchi, O Kavehei - Integration, 2009 - Elsevier
This paper presents a novel low-power majority function-based 1-bit full adder that uses
MOS capacitors (MOSCAP) in its structure. It can work reliably at low supply voltage. In this …

Design of two Low-Power full adder cells using GDI structure and hybrid CMOS logic style

V Foroutan, MR Taheri, K Navi, AA Mazreah - Integration, 2014 - Elsevier
Full adder is one of the most important digital components for which many improvements
have been made to improve its architecture. In this paper, we present two new symmetric …

[PDF][PDF] A high speed 8 transistor full adder design using novel 3 transistor XOR gates

SR Chowdhury, A Banerjee, A Roy, H Saha - International Journal of …, 2008 - Citeseer
The paper proposes the novel design of a 3T XOR gate combining complementary CMOS
with pass transistor logic. The design has been compared with earlier proposed 4T and 6T …

Novel low power full adder cells in 180nm CMOS technology

D Wang, M Yang, W Cheng, X Guan… - 2009 4th IEEE …, 2009 - ieeexplore.ieee.org
This paper proposes four low power adder cells using different XOR and XNOR gate
architectures. Two sets of circuit designs are presented. One implements full adders with 3 …