Modeling static delay variations in push–pull CMOS digital logic circuits due to electrical disturbances in the power supply
Soft errors can occur in digital integrated circuits (ICs) as a result of an electromagnetic
disturbance, such as might result from an electrical fast transient (EFT). Many soft errors …
disturbance, such as might result from an electrical fast transient (EFT). Many soft errors …
Predicting statistical characteristics of jitter due to simultaneous switching noise
Switching of logic gates is often responsible for significant power supply noise. Predicting
the jitter resulting from the power supply noise can be critical to analyze the proper operation …
the jitter resulting from the power supply noise can be critical to analyze the proper operation …
A hybrid method for signal integrity analysis of traces and vias in an infinitely large plate pair
L Ren, P Shao, K Qiu, J Lim, R Brooks… - IEEE Transactions …, 2015 - ieeexplore.ieee.org
A hybrid approach is proposed to signal integrity analysis of trace and vias in plate pair with
an infinitely large dimension. By using the domain decomposition method, trace domain and …
an infinitely large dimension. By using the domain decomposition method, trace domain and …
A Vectorless Approach for Predicting Switching Activity in a Digital Circuit
L Ren, S Sun, M Deo, J Jaffari, P Anmula… - IEEE Transactions …, 2016 - ieeexplore.ieee.org
Existing vectorless methods use a statistical approach to estimate the average number of
switching events in a digital circuit. While these methods allow one to predict the average …
switching events in a digital circuit. While these methods allow one to predict the average …