Modeling the effect of technology trends on the soft error rate of combinational logic
P Shivakumar, M Kistler, SW Keckler… - Proceedings …, 2002 - ieeexplore.ieee.org
This paper examines the effect of technology scaling and microarchitectural trends on the
rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to …
rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to …
Dual use of superscalar datapath for transient-fault detection and recovery
Diminutive devices and high clock frequency of future microprocessor generations are
causing increased concerns for transient soft failures in hardware, necessitating fault …
causing increased concerns for transient soft failures in hardware, necessitating fault …
Efficient resource sharing in concurrent error detecting superscalar microarchitectures
Previous proposals for soft-error tolerance have called for redundantly executing a program
as two concurrent threads on a superscalar microarchitecture. In a balanced superscalar …
as two concurrent threads on a superscalar microarchitecture. In a balanced superscalar …
In-register duplication: Exploiting narrow-width value for improving register file reliability
J Hu, S Wang, SG Ziavras - International Conference on …, 2006 - ieeexplore.ieee.org
Protecting the register value and its data buses is crucial to reliable computing in high-
performance microprocessors due to the increasing susceptibility of CMOS circuitry to soft …
performance microprocessors due to the increasing susceptibility of CMOS circuitry to soft …
Microarchitecture-based introspection: A technique for transient-fault tolerance in microprocessors
MK Qureshi, O Mutlu, YN Patt - 2005 International Conference …, 2005 - ieeexplore.ieee.org
The increasing transient fault rate necessitates on-chip fault tolerance techniques in future
processors. The speed gap between the processor and the memory is also increasing …
processors. The speed gap between the processor and the memory is also increasing …
A complexity-effective approach to alu bandwidth enhancement for instruction-level temporal redundancy
A Parashar, S Gurumurthi… - ACM SIGARCH Computer …, 2004 - dl.acm.org
Previous proposals for implementing instruction-level temporalredundancy in out-of-order
cores have reported a performancedegradation of upto 45% in certain applications …
cores have reported a performancedegradation of upto 45% in certain applications …
Compiler-assisted soft error detection under performance and energy constraints in embedded systems
J Hu, F Li, V Degalahal, M Kandemir… - ACM Transactions on …, 2009 - dl.acm.org
Soft errors induced by terrestrial radiation are becoming a significant concern in
architectures designed in newer technologies. If left undetected, these errors can result in …
architectures designed in newer technologies. If left undetected, these errors can result in …
Using underutilized CPU resources to enhance its reliability
A Timor, A Mendelson, Y Birk… - IEEE Transactions on …, 2008 - ieeexplore.ieee.org
Soft errors (or transient faults) are temporary faults that arise in a circuit due to a variety of
internal noise and external sources such as cosmic particle hits. Though soft errors still …
internal noise and external sources such as cosmic particle hits. Though soft errors still …
On the exploitation of narrow-width values for improving register file reliability
J Hu, S Wang, SG Ziavras - IEEE transactions on very large …, 2009 - ieeexplore.ieee.org
Protecting the register value and its data buses is crucial to reliable computing in high-
performance microprocessors due to the increasing susceptibility of CMOS circuitry to soft …
performance microprocessors due to the increasing susceptibility of CMOS circuitry to soft …
Function-inherent code checking: A new low cost on-line testing approach for high performance microprocessor control logic
We propose an on-line testing approach for the control logic of high performance
microprocessors. Rather than adding information redundancy (in the form of error detecting …
microprocessors. Rather than adding information redundancy (in the form of error detecting …