System and method for configuring a solid-state storage device with error correction coding
SM Brandenberger, T Munden, J Jedwab… - US Patent …, 2007 - Google Patents
A system for configuring solid-state storage devices comprises a solid-state storage device
and an error correction code (ECC) selection system. The ECC selection system is …
and an error correction code (ECC) selection system. The ECC selection system is …
Data storage device tester
LJ Dalphy, CE Stevens, DK Blackburn - US Patent 8,458,526, 2013 - Google Patents
2010-05-19 Assigned to WESTERN DIGITAL TECHNOLOGIES, INC. reassignment
WESTERN DIGITAL TECHNOLOGIES, INC. ASSIGNMENT OF ASSIGNORS INTEREST …
WESTERN DIGITAL TECHNOLOGIES, INC. ASSIGNMENT OF ASSIGNORS INTEREST …
Data storage device tester
CE Stevens, LJ Dalphy - US Patent 8,626,463, 2014 - Google Patents
2018-03-05 Assigned to WESTERN DIGITAL TECHNOLOGIES, INC. reassignment
WESTERN DIGITAL TECHNOLOGIES, INC. RELEASE BY SECURED PARTY (SEE …
WESTERN DIGITAL TECHNOLOGIES, INC. RELEASE BY SECURED PARTY (SEE …
Magnetic memory with error correction coding
TC Adelmann, SR Wyatt, KK Smith - US Patent 7,191,379, 2007 - Google Patents
Embodiments of the present invention are implemented in memory systems. In one
embodiment, the memory comprises an array of memory cells and a control circuit. The …
embodiment, the memory comprises an array of memory cells and a control circuit. The …
Magnetic memory including a sense result category between logic states
FA Perner, J Jedwab, JA Davis, D McIntyre… - US Patent …, 2006 - Google Patents
Embodiments of the present invention provide a magnetic memory. In one embodiment, the
magnetic memory comprises an array of memory cells configured to provide resistive states …
magnetic memory comprises an array of memory cells configured to provide resistive states …
Adapting a communication network to varying conditions
AA Hassan, C Huitema, T Kuehnel… - US Patent 8,396,041, 2013 - Google Patents
Abstract Systems and methods are disclosed for adapting a communication system to
varying conditions. Using some form of discovery protocol, the communication standards …
varying conditions. Using some form of discovery protocol, the communication standards …
Semiconductor storage device and method of operating the same
N Sakimura, T Sugibayashi, R Nebashi - US Patent 8,510,633, 2013 - Google Patents
US8510633B2 - Semiconductor storage device and method of operating the same - Google
Patents US8510633B2 - Semiconductor storage device and method of operating the same …
Patents US8510633B2 - Semiconductor storage device and method of operating the same …
Method for error correction decoding in an MRAM device (historical erasures)
JA Davis, J Jedwab, KG Paterson… - US Patent 6,990,622, 2006 - Google Patents
A magnetoresistive solid-state storage device (MRAM) employs error correction coding
(ECC) to form ECC encoded stored data. ECC encoded data is read and decoded to identify …
(ECC) to form ECC encoded stored data. ECC encoded data is read and decoded to identify …
Selective activation of error mitigation based on bit level error count
A Biswas, S Raasch, S Mukherjee - US Patent App. 11/151,818, 2007 - Google Patents
Embodiments of apparatuses and methods for selective activation of error mitigation based
on bit level error counts are disclosed. In one embodiment, an apparatus includes a plurality …
on bit level error counts are disclosed. In one embodiment, an apparatus includes a plurality …
MRAM and operation method of the same
N Sakimura, T Honda, T Sugibayashi - US Patent 7,688,617, 2010 - Google Patents
An operation method of an MRAM of the present invention is an operation method of the
MRAM in which a data write operation is carried out in a toggle write. The operation method …
MRAM in which a data write operation is carried out in a toggle write. The operation method …