Dynamic instruction reuse

A Sodani, GS Sohi - ACM SIGARCH Computer Architecture News, 1997 - dl.acm.org
This paper introduces the concept of dynamic instruction reuse. Empirical observations
suggest that many instructions, and groups of instructions, having the same inputs, are …

Slipstream processors: Improving both performance and fault tolerance

K Sundaramoorthy, Z Purser, E Rotenberg - ACM SIGPLAN Notices, 2000 - dl.acm.org
Processors execute the full dynamic instruction stream to arrive at the final output of a
program, yet there exist shorter instruction streams that produce the same overall effect. We …

[图书][B] Computer architecture techniques for power-efficiency

S Kaxiras, M Martonosi - 2008 - books.google.com
In the last few years, power dissipation has become an important design constraint, on par
with performance, in the design of new computer systems. Whereas in the past, the primary …

I-CASH: Intelligently coupled array of SSD and HDD

Q Yang, J Ren - 2011 IEEE 17th International Symposium on …, 2011 - ieeexplore.ieee.org
This paper presents a new disk I/O architecture composed of an array of a flash memory
SSD (solid state disk) and a hard disk drive (HDD) that are intelligently coupled by a special …

A case for core-assisted bottleneck acceleration in GPUs: enabling flexible data compression with assist warps

N Vijaykumar, G Pekhimenko, A Jog… - ACM SIGARCH …, 2015 - dl.acm.org
Modern Graphics Processing Units (GPUs) are well provisioned to support the concurrent
execution of thousands of threads. Unfortunately, different bottlenecks during execution and …

A theoretical study of hardware performance counters-based malware detection

K Basu, P Krishnamurthy, F Khorrami… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
Malware can range from simple adware to stealthy kernel control-flow modifying rootkits.
Although anti-virus software is popular, an ongoing cat-and-mouse cycle of anti-virus …

[PDF][PDF] BDD based decomposition of logic functions with application to FPGA synthesis

YT Lai, M Pedram, SBK Vrudhula - Proceedings of the 30th international …, 1993 - dl.acm.org
This paper presents a theory for (disjunctive and nondisjunctive) function decomposition
using the BDD representation of Boolean functions. Incompletely specified as well as multi …

[PDF][PDF] A study of slipstream processors

Z Purser, K Sundaramoorthy, E Rotenberg - Proceedings of the 33rd …, 2000 - dl.acm.org
A slipstream processor reduces the length of a running program by dynamically skipping
computation non-essential for correct forward progress. The shortened program runs faster …

Eliminating redundant fragment shader executions on a mobile gpu via hardware memoization

JM Arnau, JM Parcerisa, P Xekalakis - ACM SIGARCH Computer …, 2014 - dl.acm.org
Redundancy is at the heart of graphical applications. In fact, generating an animation
typically involves the succession of extremely similar images. In terms of rendering these …

Reducing DRAM latency at low cost by exploiting heterogeneity

D Lee - arXiv preprint arXiv:1604.08041, 2016 - arxiv.org
In modern systems, DRAM-based main memory is significantly slower than the processor.
Consequently, processors spend a long time waiting to access data from main memory …