Voxelisation algorithms and data structures: a review
Voxel-based data structures, algorithms, frameworks, and interfaces have been used in
computer graphics and many other applications for decades. There is a general necessity to …
computer graphics and many other applications for decades. There is a general necessity to …
Parallel programming models for heterogeneous many-cores: a comprehensive survey
Heterogeneous many-cores are now an integral part of modern computing systems ranging
from embedding systems to supercomputers. While heterogeneous many-core design offers …
from embedding systems to supercomputers. While heterogeneous many-core design offers …
The ARM scalable vector extension
N Stephens, S Biles, M Boettcher, J Eapen… - IEEE micro, 2017 - ieeexplore.ieee.org
This article describes the ARM Scalable Vector Extension (SVE). Several goals guided the
design of the architecture. First was the need to extend the vector processing capability …
design of the architecture. First was the need to extend the vector processing capability …
The future of microprocessors
The future of microprocessors Page 1 MAy 2011 | vOl. 54 | nO. 5 | CommunICatIons of the aCm
67 MICroProCessors—sInGLe-ChIP CoMPUters—are the building blocks of the information …
67 MICroProCessors—sInGLe-ChIP CoMPUters—are the building blocks of the information …
Massively parallel processing core with plural chains of processing elements and respective smart memory storing select data received from each chain
An accelerator System is shown that includes a plurality of processing cores. Each
processing core includes a plurality of processing chains configured to perform parallel …
processing core includes a plurality of processing chains configured to perform parallel …
High performance cellular level agent-based simulation with FLAME for the GPU
Driven by the availability of experimental data and ability to simulate a biological scale
which is of immediate interest, the cellular scale is fast emerging as an ideal candidate for …
which is of immediate interest, the cellular scale is fast emerging as an ideal candidate for …
Low-cost router microarchitecture for on-chip networks
J Kim - Proceedings of the 42nd annual IEEE/ACM …, 2009 - dl.acm.org
On-chip networks are critical to the scaling of future multi-core processors. The challenge for
on-chip network is to reduce the cost including power consumption and area while providing …
on-chip network is to reduce the cost including power consumption and area while providing …
Architecture support for accelerator-rich CMPs
This work discusses a hardware architectural support for accelerator-rich CMPs (ARC). First,
we present a hardware resource management scheme for accelerator sharing. This scheme …
we present a hardware resource management scheme for accelerator sharing. This scheme …
Charm: A composable heterogeneous accelerator-rich microprocessor
This work discusses CHARM, a Composable Heterogeneous Accelerator-Rich
Microprocessor design that provides scalability, flexibility, and design reuse in the space of …
Microprocessor design that provides scalability, flexibility, and design reuse in the space of …
Networks on chips: structure and design methodologies
The next generation of multiprocessor system on chip (MPSoC) and chip multiprocessors
(CMPs) will contain hundreds or thousands of cores. Such a many‐core system requires …
(CMPs) will contain hundreds or thousands of cores. Such a many‐core system requires …