The ability for Single Event Transients (SETs) to induce soft errors in Integrated Circuits (ICs)
was predicted for the first time by Wallmark and Marcus in the early 60's and was confirmed …

Technology Scaling and Soft Error Reliability Page 1 Technology Scaling and Soft Error
Reliability Lloyd W. Massengill Professor, Department of Electrical Engineering and Computer …

This paper presents a SET predictive methodology based on coupled MUSCA SEP3 and
electrical simulations (CADENCE tool). The method is validated by SET measurements on …

Radiation-induced multiple event transients (METs) are expected to become more frequent
than single event transients (SETs) at nanoscale CMOS technology nodes. In this paper, a …

In this paper, a novel layout technique for single-event transient (SET) mitigation based on
dummy transistors is proposed. Numerical simulations using technology computer-aided …

In this paper, a layout technique for P-hit single-event transient (SET) mitigation via source
isolation is studied by way of technology-computer-aided-design numerical simulations. The …

As technology feature size decreases, single event upset (SEU), and single event transient
(SET) dominate the radiation response of microcircuits. Multiple bit upset (MBU)(or multi cell …

As the technology scales down, space radiation induced soft errors are becoming a critical
issue for the reliability of Integrated Circuits (ICs). In this paper, we propose a novel layout …

In this paper, a novel layout technique for N-hit single-event transient (SET) mitigation that is
based on source-extension is proposed. Based on 65 nm bulk CMOS technology, both …

Heavy-ion experiments on spatially isolated inverters and densely populated inverters
demonstrate the effects of transistor density on single-event (SE) transients in bulk CMOS …