Review and critique of analytic models of MOSFET short-channel effects in subthreshold
Q Xie, J Xu, Y Taur - IEEE transactions on electron devices, 2012 - ieeexplore.ieee.org
This paper surveys, reviews, and critiques analytic models of MOSFET short-channel effects
(SCEs) in subthreshold published over the past four decades. In the first half of this paper …
(SCEs) in subthreshold published over the past four decades. In the first half of this paper …
Future CMOS scaling and reliability
C Hu - Proceedings of the IEEE, 1993 - ieeexplore.ieee.org
The goals and constraints of MOSFET scaling are reviewed, and the role of reliability
constraints is highlighted. It is concluded that judicial shrinking of MOSFET device …
constraints is highlighted. It is concluded that judicial shrinking of MOSFET device …
[图书][B] Device electronics for integrated circuits
Focusing specifically on silicon devices, the Third Edition of Device Electronics for Integrated
Circuits takes students in integrated-circuits courses from fundamental physics to detailed …
Circuits takes students in integrated-circuits courses from fundamental physics to detailed …
[图书][B] Distortion analysis of analog integrated circuits
P Wambacq, WMC Sansen - 2013 - books.google.com
The analysis and prediction of nonlinear behavior in electronic circuits has long been a topic
of concern for analog circuit designers. The recent explosion of interest in portable …
of concern for analog circuit designers. The recent explosion of interest in portable …
Elementary scattering theory of the Si MOSFET
M Lundstrom - IEEE Electron Device Letters, 1997 - ieeexplore.ieee.org
A simple one-flux scattering theory of the silicon MOSFET is introduced. Current-voltage (IV)
characteristics are expressed in terms of scattering parameters rather than a mobility. For …
characteristics are expressed in terms of scattering parameters rather than a mobility. For …
Nanoscale cmos
This paper examines the apparent limits, possible extensions, and applications of CMOS
technology in the nanometer regime. Starting from device scaling theory and current industry …
technology in the nanometer regime. Starting from device scaling theory and current industry …
Tradeoffs and optimization in analog CMOS design
DM Binkley - 2007 14th International Conference on Mixed …, 2007 - ieeexplore.ieee.org
The selection of drain current, inversion coefficient, and channel length for each MOS device
in an analog circuit results in significant tradeoffs in performance. The selection of inversion …
in an analog circuit results in significant tradeoffs in performance. The selection of inversion …
Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads
Dynamic voltage scaling (DVS) reduces the power consumption of processors when peak
performance is unnecessary. However, the achievable power savings by DVS alone is …
performance is unnecessary. However, the achievable power savings by DVS alone is …
Generalized scale length for two-dimensional effects in MOSFETs
We derive a new scale length for two-dimensional (2-D) effects in MOSFETs and discuss its
significance. This derivation properly takes into account the difference in permittivity …
significance. This derivation properly takes into account the difference in permittivity …
Scaling of stack effect and its application for leakage reduction
S Narendra, V De, D Antoniadis… - Proceedings of the …, 2001 - dl.acm.org
Technology scaling demands a decrease in both Vdd and Vt to sustain historical delay
reduction, while restraining active power dissipation. Scaling of Vt however leads to …
reduction, while restraining active power dissipation. Scaling of Vt however leads to …