A 3.5 GHz digital fractional-N PLL in 65 nm CMOS technology is presented that achieves
phase noise and spurious tone performance comparable to those of a high-performance …

This article presents a wide input-range delay chain based time amplifier (TA) and its
application to a 6.5-GHz digital fractional-N phase-locked loop (PLL). The TA includes a …

A frequency-to-digital-converter based PLL (FDC-PLL) that implements the functionality of a
charge pump and analog-to-digital converter (ADC) with a dual-mode ring oscillator (DMRO) …

Increasing a PLL's reference frequency offers significant performance advantages, but doing
so by increasing the PLL's crystal oscillator frequency is not a viable option in many …

Digital-to-time converter (DTC) based quantization noise cancellation (QNC) has recently
been shown to enable excellent fractional-PLL performance, but it requires a highly-linear …

This paper describes all-digital enhancements for digital fractional-N phase-locked loops
(PLLs) based on delta-sigma (ΔΣ) frequency-to-digital converters (FDCs). The …

Mismatches among frequency control elements in digitally-controlled oscillators can be a
significant source of phase error in digital phase-locked loops (PLLs). This paper presents a …

Phase-locked loops (PLLs) are critical components in modern electronics communication
systems, where they are used to synthesize local oscillator signals for modulation and …

The pull-in process is a mechanism where phaselocked loop acquires lock state. It is known
as the highest range of frequency where the phase locked loop (PLL) has a separatrix cycle …

Phase-locked loops (PLLs) are critical components in modern electronics communication
systems, where they are used to synthesize local oscillator signals for modulation and …