In recent years, it has been witnessed that the systolic array is a successful architecture for
DNN hardware accelerators. However, the design of systolic arrays also encountered many …

As machine learning and AI continue to rapidly develop, and with the ever-closer end of
Moore's law, new avenues and novel ideas in architecture design are being created and …

Deep Learning (DL) acceleration support in CPUs has recently gained a lot of traction, with
several companies (Arm, Intel, IBM) announcing products with specialized matrix engines …

In the past two years, various graph convolution neural networks (GCNs) accelerators have
emerged, each with their own characteristics, but their common disadvantage is that the …

Convolution is a fundamental and computationally expensive primitive and finds ubiquitous
in deep neural networks (DNNs). The evolving DNNs have spurred the emergence of …

Efficient image processing is increasingly crucial in constrained embedded and real-time
platforms, especially in emerging applications such as Autonomous Driving (AD) or …

Computing latency is an important system metric for Deep Neural Networks (DNNs)
accelerators. To reduce latency, this work proposes LV, a latency-versatile floating-point …

Exploiting sparsity in deep neural networks (DNNs) has been a promising area to meet the
growing computation need of modern DNNs. However, in practice, sparse DNN acceleration …

Dilated and transposed convolutions are widely used in modern convolutional neural
networks (CNNs). These kernels are used extensively during CNN training and inference of …

Recognizing the explosive increase in the use of DNN-based applications, several industrial
companies developed a custom ASIC (eg, Google TPU, IBM RaPiD, Intel NNP-I/NNP-T) and …