Power distribution network for 3D logic and memory

L Liebmann, J Smith, AJ Devilliers, K Tapily - US Patent 11,114,381, 2021 - Google Patents
A semiconductor device is provided. The semiconductor device includes a transistor stack
having a plurality of transistor pairs that are stacked over a substrate. Each transistor pair of …

Layout construction for addressing electromigration

SH Rasouli, A Datta, O Kwon - US Patent 10,580,774, 2020 - Google Patents
2007/0030741 A1 2008/0086709 Al 2009/0164964 A1 2009/0278207 Al 2011/0241126 A1
2012/0176193 A1 2012/0221759 Al 2012/0273849 Al 2013/0055184 A1 2013/0069170 A1 …

Layout construction for addressing electromigration

SH Rasouli, MJ Brunolli, CSA Hau-Riege… - US Patent …, 2020 - Google Patents
(57) ABSTRACT A CMOS device with a plurality of PMOS transistors and a plurality of
NMOS transistors includes a first interconnect and a second interconnect on an interconnect …

Power distribution network for 3D logic and memory

L Liebmann, J Smith, AJ Devilliers, K Tapily - US Patent 11,616,020, 2023 - Google Patents
(57) ABSTRACT A semiconductor device includes a transistor stack. The transistor stack has
a plurality of transistors that are stacked over a substrate. Each of the plurality of transistors …

Layout construction for addressing electromigration

SH Rasouli, MJ Brunolli, CSA Hau-Riege… - US Patent …, 2022 - Google Patents
(57) ABSTRACT A CMOS device with a plurality of PMOS transistors each having a PMOS
drain and a plurality of NMOS transistors each having an NMOS drain includes a first …

Layout construction for addressing electromigration

SH Rasouli, A Datta, O Kwon - US Patent 11,437,375, 2022 - Google Patents
A first interconnect on an interconnect level connects a first subset of PMOS drains together
of a CMOS device. A second interconnect on the interconnect level connects a second …