Source-level performance, energy, reliability, power and thermal (PERPT) simulation
With ever increasing design complexities, traditional cycle-accurate or instruction-set
simulations are often too slow or too inaccurate for system prototyping in early design …
simulations are often too slow or too inaccurate for system prototyping in early design …
[PDF][PDF] Host-compiled reliability modeling for fast estimation of architectural vulnerabilities
Due to ever increasing design complexities and continued technology scaling, reliability
concerns due to single event upsets have become a key metric in electronic system design …
concerns due to single event upsets have become a key metric in electronic system design …
Network-level design space exploration of resource-constrained networks-of-systems
Z Zhao, KM Barijough, A Gerstlauer - ACM Transactions on Embedded …, 2020 - dl.acm.org
Driven by recent advances in networking and computing technologies, distributed
application scenarios are increasingly deployed on resource-constrained processing …
application scenarios are increasingly deployed on resource-constrained processing …
RSVP: Soft error resilient power savings at near-threshold voltage using register vulnerability
With the ever-growing scaling of computing capability, computing systems like
supercomputers and embedded systems are bounded by limited power nowadays. Upon …
supercomputers and embedded systems are bounded by limited power nowadays. Upon …
[PDF][PDF] D3. 1–Report on major classes of hard-ware components
As described in the DoW, in Task T3. 1, the five major classes of hardware components
(processors, accelerators, memories, peripherals, interconnects) will be analyzed and …
(processors, accelerators, memories, peripherals, interconnects) will be analyzed and …
[图书][B] EDA Techniques for the Efficient Analysis of Variability in Deeply-Scaled Transistors
D Stamoulis - 2015 - search.proquest.com
As transistor dimensions scale down to the order of several atoms, digital systems are
exhibiting alarming performance degradation and significantly reduced yield due to …
exhibiting alarming performance degradation and significantly reduced yield due to …
[PDF][PDF] Design and Implementation of Optimized Dual Port Register File Bit Cell
B BIT - International Journal of Scientific and Research … - Citeseer
The memory bit cell is the most important block of any memory. It defines memory
specifications and occupies a major portion of the area in any memory. Power performance …
specifications and occupies a major portion of the area in any memory. Power performance …