We introduce the first microarchitectural side channel attacks that leverage contention on the
CPU ring interconnect. There are two challenges that make it uniquely difficult to exploit this …

Responding to the" datacenter tax" and" killer microseconds" problems for memory-intensive
datacenter applications, diverse solutions including Smart NIC-based ones have been …

Memory access is the major bottleneck in realizing multi-hundred-gigabit networks with
commodity hardware, hence it is essential to make good use of cache memory that is a …

Cache side-channel attacks lead to severe security threats to the settings where a CPU is
shared across users, eg, in the cloud. The majority of attacks rely on sensing the micro …

While the current literature typically focuses on load-balancing among multiple servers, in
this paper, we demonstrate the importance of load-balancing within a single machine …

Unarbitrated contention over shared resources at different levels of the memory hierarchy
represents a major source of temporal interference. Hardware manufacturers are …

We present nanoBench, a tool for evaluating small microbenchmarks using hardware
performance counters on Intel and AMD x86 systems. Most existing tools and libraries are …

Prefetching which predicts future memory accesses and preloads them from main memory,
is a widely-adopted technique to overcome the processor-memory performance gap …

We present PacketMill, a system for optimizing software packet processing, which (i)
introduces a new model to efficiently manage packet metadata and (ii) employs code …

Large-scale online services are commonly structured as a network of software tiers, which
communicate over the datacenter network using RPCs. Ongoing trends towards software …