A floating random walk (FRW) solver, called RWCap, is presented for the capacitance
extraction of very-large-scale integration (VLSI) interconnects. An approach, including the …

The main goal of writing this book was to present a methodological and algorithmic
perspective on the field-solver-based parasitic extraction of integrated circuits (ICs) …

Electronic design automation (EDA) is a software technology that attempts to let computers
undertake chip design tasks so that we can handle complexities beyond manual design …

In the capacitance extraction with the floating random walk (FRW) algorithm, the space
management approach is required to facilitate finding the nearest conductor. The Octree and …

3-D integrated circuits (3-D ICs) make use of the vertical dimension for smaller footprint,
higher speed, lower power consumption, and better timing performance. In 3-D ICs, the inter …

To enable the capacitance extraction of chip-scale large VLSI layout using the floating
random walk (FRW) algorithm, two techniques are proposed. The first one is a virtual …

In this paper we review some of the state of the art techniques for parasitic interconnect
extraction in the presence of random geometrical variations due to uncertainties in the …

The non-Manhattan conductor geometry existing in some capacitance extraction problems
brings difficulty to the floating random walk (FRW) method using cubic transition domains. In …

With the advancement of fabrication technology, the electrostatic coupling has increasing
impact on the performance of very large-scale integrated (VLSI) circuits and micro …

In this paper, we propose a hierarchical algorithm to compute the 3-D capacitances of a
large number of topologically different layout configurations that are all assembled from the …