Low-power SAR ADC design: Overview and survey of state-of-the-art techniques
This paper presents an overview for low-power successive approximation register (SAR)
analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and …
analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and …
Integrated circuits and electrode interfaces for noninvasive physiological monitoring
This paper presents an overview of the fundamentals and state of the-art in noninvasive
physiological monitoring instrumentation with a focus on electrode and optrode interfaces to …
physiological monitoring instrumentation with a focus on electrode and optrode interfaces to …
A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS
A 1.2 V 10-bit 100 MS/s Successive Approximation (SA) ADC is presented. The scheme
achieves high-speed and low-power operation thanks to the reference-free technique that …
achieves high-speed and low-power operation thanks to the reference-free technique that …
A 10-bit Charge-Redistribution ADC Consuming 1.9 W at 1 MS/s
M Van Elzakker, E van Tuijl, P Geraedts… - IEEE Journal of Solid …, 2010 - ieeexplore.ieee.org
This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits
from technology scaling. It meets extremely low power requirements by using a charge …
from technology scaling. It meets extremely low power requirements by using a charge …
[图书][B] Analog-to-digital conversion
MJM Pelgrom, MJM Pelgrom - 2013 - Springer
Several classifications exist of Nyquist-rate analog-to-digital converters. In this chapter the
converters are subdivided in parallel search, sequential search, and linear search. Each of …
converters are subdivided in parallel search, sequential search, and linear search. Each of …
A 10-b 50-MS/s 820-W SAR ADC With On-Chip Digital Calibration
M Yoshioka, K Ishikawa, T Takayama… - IEEE transactions on …, 2010 - ieeexplore.ieee.org
This 10-b 50-MSamples/s SAR analog-to-digital converter (ADC) features on-chip digital
calibration techniques, comparator offset cancellation, a capacitor digital-to-analog …
calibration techniques, comparator offset cancellation, a capacitor digital-to-analog …
A 7 bit, 3.75 ps resolution two-step time-to-digital converter in 65 nm CMOS using pulse-train time amplifier
In this paper, a novel pulse-train time amplifier is proposed that achieves linear, accurate,
and programmable gain for a wide input range. Using the proposed pulse-train time …
and programmable gain for a wide input range. Using the proposed pulse-train time …
Characterization of human body-based thermal and vibration energy harvesting for wearable devices
Energy harvesting is an important enabling technology necessary to unleash the next shift in
mm-scale and μW power computing devices, especially for wireless sensor nodes. Energy …
mm-scale and μW power computing devices, especially for wireless sensor nodes. Energy …
A 9 bit, 1.12 ps resolution 2.5 b/stage pipelined time-to-digital converter in 65 nm CMOS using time-register
In this paper, a 2.5 b/stage pipelined time-to-digital converter (TDC) is presented. For
pipelined operation, a novel time-register is proposed which is capable of storing, adding …
pipelined operation, a novel time-register is proposed which is capable of storing, adding …
Split capacitor DAC mismatch calibration in successive approximation ADC
Y Chen, X Zhu, H Tamura, M Kibune… - IEICE transactions on …, 2010 - search.ieice.org
Charge redistribution based successive approximation (SA) analog-to-digital converter
(ADC) has the advantage of power efficiency. Split capacitor digital-to-analog converter …
(ADC) has the advantage of power efficiency. Split capacitor digital-to-analog converter …