This paper presents a technique called supply boosting for designing sub-1V analog/mixed-
signal circuits. Supply boosting technique (SBT) is suitable for sub-micron CMOS processes …

This paper presents a new very low-power, low-voltage successive approximation analog to
digital converter (SAR ADC) design based on supply boosting technique. The supply …

Low‐voltage high‐precision comparators are the main building blocks of many low‐power
mixed‐mode electronic devices. In this paper, a rail‐to‐rail high‐precision comparator is …

Purpose In parallel sampling method, the size of the sampling capacitor is reduced to
improve the bandwidth of the ADC. Design/methodology/approach Various low-power …

Reduced voltage head room availability for input signal swing is one of the major
bottlenecks in the design of circuits operating with low supply voltages which attracts …

As clocking speeds increase, it becomes more and more important to be able to generate”
clean”, low-jitter clock signals. Traditionally, PLLs have been one of the most commonly …

This paper presents analytical solutions for high efficiency maximum power point tracking
boost converters. Employing analytical approach, it is shown that insertion of a capacitor in …

基于预放大锁存快速比较理论, 提出了一种新型高速低功耗CM0S 比较器的电路拓扑.
采用典型的0.35 m/3.3 V 硅CM0S 工艺模型, 用Cadence 软件进行模拟仿真, 比较器延迟时间为 …

The design of a 0.8 V 1GHz dynamic comparator in digital 90nm CMOS technology is
presented. The work shows that low voltage, low power and high speed analog circuits are …

Analog-to-digital converters (ADCs) are ubiquitous and indispensable components in an
Internet of Things (IoT) world, bridging the analog to the digital, and FLASH ADCs have long …