In this work, we present a novel 8T static random access memory (SRAM)-based compute-in-
memory (CIM) macro for processing neural networks with high energy efficiency. The …

This work demonstrates a programmable in-memory-computing (IMC) inference accelerator
for scalable execution of neural network (NN) models, leveraging a high-signal-to-noise …

This paper presents a detailed overview of sparsity exploitation in deep neural network
(DNN) accelerators. Despite the algorithmic advancements which drove DNNs to become …

Recently, on-device training has become crucial for the success of edge intelligence.
However, frequent data movement between computing units and memory during training …

This work introduces a digital SRAM-based near-memory compute macro for DNN
inference, improving on-chip weight memory capacity and area efficiency compared to state …

Memory latency and bandwidth are significant bottlenecks in designing in-memory indexes.
Processing-in-memory (PIM), an emerging hardware design approach, alleviates this …

Deep learning (DL) has proven to be one of the most pivotal components of machine
learning given its notable performance in a variety of application domains. Neural networks …

This article reports a keyword-spotting (KWS) chip for voice-controlled devices. It features a
number of techniques to enhance the performance, area, and power efficiencies: 1) a fast …

Self-attention-based transformers have outperformed recurrent and convolutional neural
networks (RNN/CNNs) in many applications. Despite the effectiveness, calculating self …

This article reports a passive analog feature extractor for realizing an area-and-power-
efficient voice activity detector (VAD) for voice-control edge devices. It features a switched …