Memory latency and bandwidth are progressing at a much slower pace than processor
performance. In this paper, we describe and evaluate the performance of three variations of …

Prefetching, ie, exploiting the overlap of processor computations with data accesses, is one
of several approaches for tolerating memory latencies. Prefetching can be either hardware …

This paper studies and compares the use of data prefetching and an alternative mechanism,
data forwarding, for reducing memory latency due to interprocessor communication in cache …

We are attacking the memory bottleneck by building a" smart" memory controller that
improves effective memory bandwidth, bus utilization, and cache efficiency by letting …

This paper presents the concept of dynamic control independence (DCl) and shows how it
can be detected and exploited in an out-of-order superscalar processor to reduce the …

Compiler-directed cache prefetching has the potential to hide much of the high memory
latency seen by current and future high-performance processors. However, prefetching is …

Both hardware and software prefetching have been shown to be effective in tolerating the
large memory latencies inherent in shared-memory multiprocessors; however, both types of …

Beyond data caching, data prefetching is by far the most effective way to address the
memory access bottleneck associated with high-performance processors. This is particularly …

This paper presents the results for the verification of the S3. mp cache coherence protocol.
The S3. mp protocol uses a distributed directory with limited number of pointers and …

Memory latency has always been a major issue in shared-memory multiprocessors and high-
speed systems. This is even more true as the gap between processor and memory speeds …