A survey of software techniques for using non-volatile memories for storage and main memory systems

S Mittal, JS Vetter - IEEE Transactions on Parallel and …, 2015 - ieeexplore.ieee.org
Non-volatile memory (NVM) devices, such as Flash, phase change RAM, spin transfer
torque RAM, and resistive RAM, offer several advantages and challenges when compared …

The landscape of exascale research: A data-driven literature analysis

S Heldens, P Hijma, BV Werkhoven… - ACM Computing …, 2020 - dl.acm.org
The next generation of supercomputers will break the exascale barrier. Soon we will have
systems capable of at least one quintillion (billion billion) floating-point operations per …

Hello ADIOS: the challenges and lessons of developing leadership class I/O frameworks

Q Liu, J Logan, Y Tian, H Abbasi… - Concurrency and …, 2014 - Wiley Online Library
Applications running on leadership platforms are more and more bottlenecked by storage
input/output (I/O). In an effort to combat the increasing disparity between I/O throughput and …

Characterizing and modeling non-volatile memory systems

Z Wang, X Liu, J Yang, T Michailidis… - 2020 53rd Annual …, 2020 - ieeexplore.ieee.org
Scalable server-grade non-volatile RAM (NVRAM) DIMMs became commercially available
with the release of Intel's Optane DIMM. Recent studies on Optane DIMM systems unveil …

The SIMNET virtual world architecture

J Calvin, A Dickens, B Gaines… - Proceedings of IEEE …, 1993 - ieeexplore.ieee.org
Many tools and techniques have been developed to address specific aspects of interacting
in a virtual world. Few have been designed with an architecture that allows large numbers of …

Hermes: a heterogeneous-aware multi-tiered distributed I/O buffering system

A Kougkas, H Devarajan, XH Sun - Proceedings of the 27th International …, 2018 - dl.acm.org
Modern High-Performance Computing (HPC) systems are adding extra layers to the memory
and storage hierarchy named deep memory and storage hierarchy (DMSH), to increase I/O …

Optimizing checkpoints using nvm as virtual memory

S Kannan, A Gavrilovska, K Schwan… - 2013 IEEE 27th …, 2013 - ieeexplore.ieee.org
Rapid checkpointing will remain key functionality for next generation high end machines.
This paper explores the use of node-local nonvolatile memories (NVM) such as phase …

[图书][B] Parallel programming for modern high performance computing systems

P Czarnul - 2018 - books.google.com
In view of the growing presence and popularity of multicore and manycore processors,
accelerators, and coprocessors, as well as clusters using such computing devices, the …

A user-level infiniband-based file system and checkpoint strategy for burst buffers

K Sato, K Mohror, A Moody, T Gamblin… - 2014 14th IEEE/ACM …, 2014 - ieeexplore.ieee.org
Checkpoint/Restart is an indispensable fault tolerance technique commonly used by high-
performance computing applications that run continuously for hours or days at a time …

Harmonia: An interference-aware dynamic I/O scheduler for shared non-volatile burst buffers

A Kougkas, H Devarajan, XH Sun… - 2018 IEEE International …, 2018 - ieeexplore.ieee.org
Modern HPC systems employ burst buffer installations to reduce the peak I/O requirements
for external storage and deal with the burstiness of I/O in modern scientific applications …