Rowpress: Amplifying read disturbance in modern dram chips

H Luo, A Olgun, AG Yağlıkçı, YC Tuğrul… - Proceedings of the 50th …, 2023 - dl.acm.org
Memory isolation is critical for system reliability, security, and safety. Unfortunately, read
disturbance can break memory isolation in modern DRAM chips. For example, RowHammer …

Nethammer: Inducing rowhammer faults through network requests

M Lipp, M Schwarz, L Raab, L Lamster… - 2020 IEEE European …, 2020 - ieeexplore.ieee.org
In this paper, we present Nethammer, a remote Rowhammer attack without a single attacker-
controlled line of code on the targeted system, ie, not even JavaScript. Nethammer works on …

ChargeCache: Reducing DRAM latency by exploiting row access locality

H Hassan, G Pekhimenko, N Vijaykumar… - … Symposium on High …, 2016 - ieeexplore.ieee.org
DRAM latency continues to be a critical bottleneck for system performance. In this work, we
develop a low-cost mechanism, called Charge Cache, that enables faster access to recently …

Translation-triggered prefetching

A Bhattacharjee - Proceedings of the Twenty-Second International …, 2017 - dl.acm.org
We propose translation-enabled memory prefetching optimizations or TEMPO, a low-
overhead hardware mechanism to boost memory performance by exploiting the operating …

Focal pre-correction of projected image for deblurring screen image

Y Oyamada, H Saito - 2007 IEEE Conference on Computer …, 2007 - ieeexplore.ieee.org
We propose a method for reducing out-of-focus blur caused by projector projection. In this
method, we estimate the Point-Spread-Function (PSF) of the out-of-focus blur in the image …

Page policy control with memory partitioning for DRAM performance and power efficiency

M Xie, D Tong, Y Feng, K Huang… - … Symposium on Low …, 2013 - ieeexplore.ieee.org
DRAM performance and power efficiency considerations are becoming increasingly
important. Bank partitioning partitions memory banks among cores and eliminates inter …

Tackling memory access latency through dram row management

S Srikanth, L Subramanian, S Subramoney… - Proceedings of the …, 2018 - dl.acm.org
Memory latency is a critical bottleneck in today's systems. The organization of the DRAM
main memory necessitates sensing and reading an entire row (around 4KB) of data in order …

Happy: Hybrid address-based page policy in drams

M Ghasempour, A Jaleel, JD Garside… - Proceedings of the …, 2016 - dl.acm.org
Memory controllers have used static page closure policies to decide whether a row should
be left open, open-page policy, or closed immediately, close-page policy, after the row has …

A predictor-based power-saving policy for dram memories

G Thomas, K Chandrasekar, B Åkesson… - 2012 15th Euromicro …, 2012 - ieeexplore.ieee.org
Reducing power/energy consumption is an important goal for all computer systems, from
servers to battery-driven hand-held devices. To achieve this goal, the energy consumption of …

A dynamic row-buffer management policy for multimedia applications

TA Alawneh - 2019 27th Euromicro International Conference on …, 2019 - ieeexplore.ieee.org
The DRAM-based main memory performance is lagging far behind the performance of
modern processors. Achieving the highest possible performance of memory-bound …