Nanoelectronics is changing the way the world communicates, and is transforming our daily
lives. Continuing Moore's law and miniaturization of low-power semiconductor chips with …

Semiconductor logic and memory technology development continues to push the limits of
process complexity and cost, especially as the industry migrates to the 5 nm node and …

Patterning at 10 nm and sub-10 nm technology nodes is one of the key challenges for the
semiconductor industry. Several patterning techniques are under investigation to enable the …

At the 5 nm technology node there are competing strategies for patterning: high-NA EUV,
double patterning 0.33 NA EUV and a combination of optical self-aligned solutions with …

Spacer multi patterning process continues to be a key enabler of future design shrinks in
DRAM and NAND process flows. Improving Critical Dimension Uniformity (CDU) for main …

This paper demonstrates the synergy between X-rays techniques and scatterometry, and the
benefits to combine the data to improve the accuracy and precision for in-line metrology …

EUV based patterning is one of the frontrunner candidates enabling scaling for future
technology nodes. However it poses the common challenges of 'pattern roughness' and …

En microélectronique, l'augmentation de la densité des composants est la solution
principale pour améliorer la performance des circuits. Ainsi, la taille des structures définies …

In the 14nm FinFET (Fin-shaped Field-Effect Transistor) node, SADP (Self-Aligned Double
Patterning) technology has been introduced to produce Fin because of the exposure limit of …