High-performance accurate and approximate multipliers for FPGA-based hardware accelerators
Multiplication is one of the widely used arithmetic operations in a variety of applications,
such as image/video processing and machine learning. FPGA vendors provide high …
such as image/video processing and machine learning. FPGA vendors provide high …
AppAxO: Designing Application-specific Approximate Operators for FPGA-based Embedded Systems
Approximate arithmetic operators, such as adders and multipliers, are increasingly used to
satisfy the energy and performance requirements of resource-constrained embedded …
satisfy the energy and performance requirements of resource-constrained embedded …
[HTML][HTML] A modular technique of Booth encoding and Vedic multiplier for low-area and high-speed applications
CM Kalaiselvi, RS Sabeenian - Scientific Reports, 2023 - nature.com
A technique for efficiently multiplying two signed numbers using limited area and high speed
is presented in this paper. This work uses both the Booth and Vedic multiplication sutra …
is presented in this paper. This work uses both the Booth and Vedic multiplication sutra …
Energy efficient logarithmic-based approximate divider for ASIC and FPGA-based implementations
The main focus of approximate dividers has been on ASIC-based designs. However, for
emerging applications, there is a need to design approximate arithmetic units compatible …
emerging applications, there is a need to design approximate arithmetic units compatible …
AxOTreeS: A Tree Search Approach to Synthesizing FPGA-based Approximate Operators
Approximate computing (AxC) provides the scope for achieving disproportionate gains in a
system's power, performance, and area (PPA) metrics by leveraging an application's …
system's power, performance, and area (PPA) metrics by leveraging an application's …
[HTML][HTML] Energy computation and multiplier-less implementation of the two-dimensional FitzHugh–Nagumo (FHN) neural circuit
Z Tabekoueng Njitacke, G Sriram, K Rajagopal… - The European Physical …, 2023 - Springer
In this work, with the aim of reducing the cost of the implementation of the traditional 2D FHN
neuron circuit, a pair of diodes connected in an anti-parallel direction is used to replace the …
neuron circuit, a pair of diodes connected in an anti-parallel direction is used to replace the …
Design of leading zero counters on FPGAs
This letter presents a novel leading zero counter (LZC) able to efficiently exploits the
hardware resources available within state-of-the-art FPGA devices to achieve high-speed …
hardware resources available within state-of-the-art FPGA devices to achieve high-speed …
FPGA-based hardware-accelerated design of linear prediction analysis for real-time speech signal
Linear prediction analysis is a crucial technique used in speech coding to compress speech
signals and facilitate their reliable transmission over limited bandwidth or storage space …
signals and facilitate their reliable transmission over limited bandwidth or storage space …
Multi-precision deep neural network acceleration on fpgas
Quantization is a promising approach to reduce the computational load of neural networks.
The minimum bit-width that preserves the original accuracy varies significantly across …
The minimum bit-width that preserves the original accuracy varies significantly across …
State-of-art analysis of multiplier designs for image processing and convolutional neural network applications
Z Aizaz, K Khare - 2022 International Conference for …, 2022 - ieeexplore.ieee.org
Recently, due to the immense growth of computing power, image processing and
Convolutional neural networks (CNN) have regained gigantic attention because of the …
Convolutional neural networks (CNN) have regained gigantic attention because of the …