A survey of leakage reduction techniques in CMOS digital circuits for nanoscale regime
VK Sharma - Australian journal of electrical and electronics …, 2021 - Taylor & Francis
The battery-driven portable systems are the lifeline of the modern era. Very large-scale
integration (VLSI) designers are continuously working to enhance the performance of the …
integration (VLSI) designers are continuously working to enhance the performance of the …
A new circuit-level technique for leakage and short-circuit power reduction of static logic gates in 22-nm CMOS technology
M Moradinezhad Maryan, M Amini-Valashani… - Circuits, Systems, and …, 2021 - Springer
The leakage power, aka static power, increases in deep-submicron technologies due to
short-channel effects. This article proposes a novel input-controlled leakage restrainer …
short-channel effects. This article proposes a novel input-controlled leakage restrainer …
Design of novel SRAM cell using hybrid VLSI techniques for low leakage and high speed in embedded memories
K Gavaskar, US Ragupathy, V Malini - Wireless Personal Communications, 2019 - Springer
Static or leakage power is the dominating component of total power dissipation in deep
nanometer technologies below 90 nm, which has resulted in increase from 18% at 130 nm …
nanometer technologies below 90 nm, which has resulted in increase from 18% at 130 nm …
Robust logic circuits design using SOI shorted-gate FinFETs
The scaling of planar Metal Oxide Semiconductor Field Effect Transistor (MOSFET)
technology has reached to its extremity. Double Gate (DG) device was introduced to derive …
technology has reached to its extremity. Double Gate (DG) device was introduced to derive …
Design and simulation of FinFET circuits at different technologies
VK Sharma - 2021 6th International Conference on Inventive …, 2021 - ieeexplore.ieee.org
Power dissipation and propagation delay are the main barriers in the progress of electronics
industry as it leads toward the Nanoscale regime of transistor and mainly transistor …
industry as it leads toward the Nanoscale regime of transistor and mainly transistor …
Leakage power reduction in CMOS logic circuits using stack ONOFIC technique
C Kumar, AS Mishra, VK Sharma - 2018 Second International …, 2018 - ieeexplore.ieee.org
Nowadays the power dissipation has become one of the problems of CMOS VLSI circuit
design. High power dissipation is not regarded as good when it comes to the battery lifespan …
design. High power dissipation is not regarded as good when it comes to the battery lifespan …
A novel low power technique for FinFET domino OR logic
Excessive scaling of complementary metal oxide semiconductor (CMOS) technology is the
main reason of large power dissipation in electronic circuits. Very large-scale integration …
main reason of large power dissipation in electronic circuits. Very large-scale integration …
Energy efficient and variability immune adder circuits using short gate FinFET INDEP technique at 10nm technology node
Due to the continuous scaling of MOSFET (Metal Oxide Semiconductor Field-Effect
Transistor) devices over the past few decades, power consumption has increased …
Transistor) devices over the past few decades, power consumption has increased …
Reliable and ultra-low power approach for designing of logic circuits
The principal design concern in today's very large-scale integration (VLSI) industry is power
dissipation. Power dissipation in a chip rises reliability issues. Static power dissipation …
dissipation. Power dissipation in a chip rises reliability issues. Static power dissipation …
Circuits implementations using carbon nanotube field-effect transistor nanotechnology
M Maqbool, VK Sharma - Engineering Research Express, 2024 - iopscience.iop.org
Device scaling is a pivotal aspect in the field of electronics, aimed at enhancing the
performance of integrated circuits (ICs) by reducing the dimensions of transistors. The …
performance of integrated circuits (ICs) by reducing the dimensions of transistors. The …