A revocable and outsourced multi-authority attribute-based encryption scheme in fog computing

S Tu, M Waqas, F Huang, G Abbas, ZH Abbas - Computer Networks, 2021 - Elsevier
Fog computing is a revolutionary technology for the next generation to bridge the gap
between cloud data centers and end-users. Fog computing is not a counterfeit for cloud …

Fast and efficient hardware architecture of Chebyshev polynomials algorithm for resisting to side channel attacks

B Madani, S Sadoudi, R Kaibou - The Journal of Supercomputing, 2025 - Springer
The field of embedded network security has seen increasing interest in developing
lightweight and efficient chaotic map-based key exchange protocols. Due to their semi …

High‐speed parallel reconfigurable Fp multipliers for elliptic curve cryptography applications

K Javeed, K Saeed, D Gregg - International Journal of Circuit …, 2022 - Wiley Online Library
Elliptic curve cryptography (ECC) protocols due to higher security strength per bit have been
widely accepted and deployed. Finite field multiplication is the most computational intensive …

High-Throughput Bilinear Pairing Processor for Server-Side FPGA Applications

J Sakamoto, D Fujimoto, R Anzai… - … Transactions on Very …, 2024 - ieeexplore.ieee.org
This study focuses on the acceleration of cryptographic pairing operations on field-
programmable gate arrays (FPGAs) for server-side applications. Previous studies on FPGA …

面向双线性对的F p 2-FIOS 模乘算法及其实现架构研究

姜占鹏, 孙铭玮, 黄海, 徐江, 刘志伟, 白瑞, 方舟… - 通信 …, 2022 - infocomm-journal.com
针对双线性对运算效率低的问题, 提出了一种面向双线性对的二次扩域细集成操作数扫描(F p 2-
FIOS) 模乘算法. 该算法通过优化二次扩域下(AB+ CD) mod P 的运算过程 …

[HTML][HTML] Coprocesador de multiplicación en/para la aceleración de emparejamientos bilineales en SoC-FPGA

R Cuiman Márquez, AJ Cabrera Sarmiento… - Ingeniería Electrónica …, 2022 - scielo.sld.cu
Los emparejamientos bilineales sobre curvas elípticas se han erigido como una potente
herramienta que permite construir diversos protocolos de seguridad para brindar vías de …

Coprocesador de multiplicación en Fp2 para la aceleración de emparejamientos bilineales en SoC-FPGA

RC Márquez, AJC Sarmiento… - Revista Científica de …, 2022 - dialnet.unirioja.es
El presente trabajo aborda el desarrollo de un coprocesador hardware para acelerar
aquellas operaciones de multiplicación en la extensión de campo Fp2 involucradas en el …