CASSER: A closed-form analysis framework for statistical soft error rate
ACC Chang, RHM Huang… - IEEE Transactions on Very …, 2012 - ieeexplore.ieee.org
CMOS designs in the deep submicrometer era require statistical methods to accurately
estimate the circuit soft error rate (SER). However, process variation increases the …
estimate the circuit soft error rate (SER). However, process variation increases the …
Effective scalable IEEE 1687 instrumentation network for fault management
Effective Scalable IEEE 1687 Instrumentation Network for Fault Management Page 1 Effective
Scalable IEEE 1687 Instrumentation Network for Fault Management Artur Jutman and …
Scalable IEEE 1687 Instrumentation Network for Fault Management Artur Jutman and …
Globally optimized robust systems to overcome scaled CMOS reliability challenges
S Mitra - Proceedings of the conference on Design, automation …, 2008 - dl.acm.org
Future system design methodologies must accept the fact that the underlying hardware will
be imperfect, and enable design of robust systems that are resilient to hardware …
be imperfect, and enable design of robust systems that are resilient to hardware …
Accurate statistical soft error rate (SSER) analysis using a quasi-Monte Carlo framework with quality cell models
For CMOS designs in sub 90nm technologies, statistical methods are necessary to
accurately estimate circuit SER considering process variations. However, due to the lack of …
accurately estimate circuit SER considering process variations. However, due to the lack of …
On soft error rate analysis of scaled CMOS designs: a statistical perspective
This paper re-examines the soft error effect caused by cosmic radiation in sub 90nm
technologies. Considering the impact of process variation, a number of statistical natures of …
technologies. Considering the impact of process variation, a number of statistical natures of …
Resilient circuits: enabling energy-efficient performance and reliability
Voltage and frequency margins necessary to ensure correct processor operation under
dynamic voltage, temperature, and aging variations result in performance and power …
dynamic voltage, temperature, and aging variations result in performance and power …
Possibilities to miss predicting timing errors in canary flip-flops
Deep submicron technologies increase parameter variations, which will make
microprocessor designs very difficult, since every variation requires a large safety margin for …
microprocessor designs very difficult, since every variation requires a large safety margin for …
Built-in proactive tuning system for circuit aging resilience
N Shah, R Samanta, M Zhang, J Hu… - … Symposium on Defect …, 2008 - ieeexplore.ieee.org
VLSI circuits in nanometer VLSI technology experience significant aging effects, which are
embodied by performance degradation over operation time. Although this degradation can …
embodied by performance degradation over operation time. Although this degradation can …
Design techniques for soft-error mitigation
M Nicolaidis - … Conference on Integrated Circuit Design and …, 2010 - ieeexplore.ieee.org
In nanometric technologies, circuits are increasingly sensitive to various kinds of
perturbations. Soft-errors, a concern in the past for space applications, became a reliability …
perturbations. Soft-errors, a concern in the past for space applications, became a reliability …
A selective replacement method for timing-error-predicting flip-flops
The aggressive technology scaling brings us new challenges, such as parameter variations,
soft errors, and device wearout. They increase unreliability of transistors and thus will …
soft errors, and device wearout. They increase unreliability of transistors and thus will …