Data Access and Storage Management for Embedded Programmable Processors gives an
overview of the state-of-the-art in system-level data access and storage management for …

A delay-locked loop (DLL) with wide-range operation and fixed latency of one clock cycle is
proposed. This DLL uses a phase selection circuit and a start-controlled circuit to enlarge …

An all-digital cycle-controlled delay-locked loop (DLL) is presented to achieve wide range
operation, fast lock and process immunity. Utilizing the cycle-controlled delay unit, the …

A 0.7-2-GHz precise multiphase delay-locked loop (DLL) using a digital calibration circuit is
presented. Incorporating with the proposed digital calibration circuit, the mismatch-induced …

A chip Set memory controller having a data Strobe mask function is disclosed. The controller
includes first through N-th memory modules operated in Synchronous with a clock Signal …

This paper presents a multiphase-output delay-locked loop (MODLL). The proposed
phase/frequency detector (PFD) utilizes a new NAND-resettable dynamic D-flip-flop (DFF) …

An initialization circuit in a delay locked loop ensures that after power up or other reset clock
edges are received by a phase detector in the appropriate order for proper operation. After …

A double data rate (DDR) synchronous dynamic RAM (SDRAM) includes delay lock loop
circuitry which is designed so as to significantly reduce the locking period associated with …

A method and a circuit configuration for implementing a double data rate feature in a
memory device capable of operating in a variable latency mode. The memory device may …

A fully integrated clock and data recovery circuit (CDR) using a multiplying shifted-averaging
delay locked loop and a rate-detection circuit is presented. It can achieve wide range and …