Reliable on-chip systems in the nano-era: Lessons learnt and future trends

J Henkel, L Bauer, N Dutt, P Gupta, S Nassif… - Proceedings of the 50th …, 2013 - dl.acm.org
Reliability concerns due to technology scaling have been a major focus of researchers and
designers for several technology nodes. Therefore, many new techniques for enhancing and …

A comparative study on adders

B Koyada, N Meghana, MO Jaleel… - … signal processing and …, 2017 - ieeexplore.ieee.org
In a digital circuit, the addition of certain number of bits is generic operation used in order to
pare the complexity of the circuit and it operation. The selection of proper adder with …

Device circuit co design of FEFET based logic for low voltage processors

S George, A Aziz, X Li, MS Kim, S Datta… - 2016 IEEE Computer …, 2016 - ieeexplore.ieee.org
Ferroelectric FETs (FEFETs) are emerging devices with potential for low power applications.
The unique feature which makes these devices suitable for ultra-low voltage operation is the …

A multi-level approach to reduce the impact of NBTI on processor functional units

T Siddiqua, S Gurumurthi - Proceedings of the 20th symposium on Great …, 2010 - dl.acm.org
NBTI is one of the most important silicon reliability problems facing processor designers
today. The impact of NBTI can be mitigated at both the circuit and microarchitecture levels. In …

Fault-tolerant carry look-ahead adder architectures robust to multiple simultaneous errors

M Valinataj - Microelectronics Reliability, 2015 - Elsevier
Currently, the demand for reliable and high performance computing is increasing due to the
enlarging susceptibility of computing circuits to different environmental effects, and the …

A novel self-checking carry lookahead adder with multiple error detection/correction

M Valinataj - Microprocessors and Microsystems, 2014 - Elsevier
Evolving processing units in complex computing systems are dealing with smaller gates and
devices which are seriously influenced by external effects such as electromagnetic noises …

Extending Moore's law via computationally error-tolerant computing

B Deng, S Srikanth, ER Hein, TM Conte… - ACM Transactions on …, 2018 - dl.acm.org
Dennard scaling has ended. Lowering the voltage supply (V dd) to sub-volt levels causes
intermittent losses in signal integrity, rendering further scaling (down) no longer acceptable …

Operand width aware hardware reuse: a low cost fault-tolerant approach to ALU design in embedded processors

M Fazeli, A Namazi, SG Miremadi… - Microelectronics …, 2011 - Elsevier
This paper presents a low cost fault-tolerant technique so called OWHR (Operand Width
Aware Hardware Reuse) to ALU design in embedded processors. The OWHR technique is …

Memory system design for ultra low power, computationally error resilient processor microarchitectures

S Srikanth, PG Rabbat, ER Hein, B Deng… - … Symposium on High …, 2018 - ieeexplore.ieee.org
Dennard scaling ended a decade ago. Energy reduction by lowering supply voltage has
been limited because of guard bands and a subthreshold slope of over 60mV/decade in …

Lizard: Energy-efficient hard fault detection, diagnosis and isolation in the ALU

S Hong, S Kim - 2010 IEEE International Conference on …, 2010 - ieeexplore.ieee.org
Digital circuits are expected to increasingly suffer from more hard faults due to technology
scaling. Especially, a single hard fault in the ALU might lead to a total failure in the …