A phase coherent fractional-N phase-locked loop synthesizer for maintaining phase
coherence of a synthesized frequency includes a phase coherent delta-sigma modulator …

A clock distribution architecture is provided in which the output clock signals from a plurality
of fractional-N PLLs have a known phase relationship because each fractional-N PLL is …

A phase discontinuity mitigation implementation within a phased lock loop (PLL) improves
throughput of a radio access technology. The throughput is improved by maintaining a …

Frequency divider techniques are disclosed which can be used to address two problems:
when an incorrect division occurs if the modulus control changes before the divide cycle is …

An apparatus is disclosed that implements frequency syn thesis with accelerated locking. In
an example aspect, the apparatus includes an oscillating signal source, a modulus …

US12113539B1 - Field programmable gate array with external phase-locked loop - Google
Patents US12113539B1 - Field programmable gate array with external phase-locked loop …

US12107587B1 - Field programmable gate array with internal phase-locked loop - Google
Patents US12107587B1 - Field programmable gate array with internal phase-locked loop …

A data synchronizer including an input stage, a driver stage, and a keeper stage. The input
stage latches input data to a data node in response to a first clock signal transition. The …

A frequency divider includes first circuitry, second circuitry, and third circuitry. The first
circuitry includes divide-by-two (div2) frequency divider circuitry, and the second circuitry …