Ultra-low energy CNFET-based ternary combinational circuits designs
RA Jaber, JM Aljaam, BN Owaydat… - IEEE …, 2021 - ieeexplore.ieee.org
The embedded systems, IoT (Internet of Things) devices, and portable electronic devices
spread very quickly recently. Most of them depend on batteries to operate. The target of this …
spread very quickly recently. Most of them depend on batteries to operate. The target of this …
Scaling trends in the soft error rate of SRAMs from planar to 5-nm FinFET
B Narasimham, V Chaudhary, M Smith… - 2021 IEEE …, 2021 - ieeexplore.ieee.org
SRAM SER measurements across technology nodes indicate that while scaling from planar
processes down to the 7-nm FinFET process provided a reduction in the per-bit SER at …
processes down to the 7-nm FinFET process provided a reduction in the per-bit SER at …
A vertical combo spacer to optimize electrothermal characteristics of 7-nm nanosheet gate-all-around transistor
R Liu, X Li, Y Sun, Y Shi - IEEE Transactions on Electron …, 2020 - ieeexplore.ieee.org
In this article, the impact of self-heating effect (SHE) on nanosheet gate-all-around (GAA)
transistor with a vertical combo spacer and different underlap/overlap channels is studied by …
transistor with a vertical combo spacer and different underlap/overlap channels is studied by …
Design and development of efficient SRAM cell based on FinFET for low power memory applications
Stationary random‐access memory (SRAM) undergoes an expansion stage, to repel
advanced process variation and support ultra‐low power operation. Memories occupy more …
advanced process variation and support ultra‐low power operation. Memories occupy more …
Limits to the Energy Efficiency of CMOS Microprocessors
CMOS microprocessors have achieved massive energy efficiency gains but may reach limits
soon. This paper presents an approach to estimating the limits on the maximum floating …
soon. This paper presents an approach to estimating the limits on the maximum floating …
Single-Event Upset Cross-Section Trends for D-FFs at the 5-and 7-nm Bulk FinFET Technology Nodes
At each advanced technology node, it is crucial to characterize and understand the
mechanisms affecting performance and reliability. Scaling for all nodes prior to the 5-nm …
mechanisms affecting performance and reliability. Scaling for all nodes prior to the 5-nm …
Single-event latchup in a 7-nm bulk FinFET technology
Terrestrial neutron and alpha particle irradiation data for a 7-nm bulk FinFET technology
reveal the persisting reliability threat single-event latchup (SEL) poses to advanced …
reveal the persisting reliability threat single-event latchup (SEL) poses to advanced …
Soft error characterization of D-FFs at the 5-nm bulk FinFET technology for the terrestrial environment
Soft error rates (SER) are characterized for the 5-nm bulk FinFET D flip-flops for alpha
particles, thermal neutrons, and high-energy neutrons as a function of supply voltage. At …
particles, thermal neutrons, and high-energy neutrons as a function of supply voltage. At …
Three-dimensional TID hardening design for 14 nm node SOI FinFETs
P Lu, C Yang, Y Li, B Li, Z Han - Eng, 2021 - mdpi.com
The fin field-effect transistor (FinFET) has been the mainstream technology on the VLSI
platform since the 22 nm node. The silicon-on-insulator (SOI) FinFET, featuring low power …
platform since the 22 nm node. The silicon-on-insulator (SOI) FinFET, featuring low power …
NSFET performance optimization through SiGe channel design-A simulation study
SL Cheng, C Li, XY Dong, SS Lv, HL You - Microelectronics Reliability, 2023 - Elsevier
In this article, NSFET performances including DC electrical characteristics, analog/RF
metrics and NBTI degradation are studied using 3D fully-calibrated TCAD simulation …
metrics and NBTI degradation are studied using 3D fully-calibrated TCAD simulation …