Rail to Rail ICMR and High Performance ULV Standard-Cell-Based Comparator for Biomedical and IoT Applications

R Della Sala, F Centurelli, G Scotti, G Palumbo - IEEE Access, 2024 - ieeexplore.ieee.org
In this paper a novel ultra-low voltage (ULV) standard-cell-based comparator which provides
rail-to-rail input common-mode range (ICMR) is presented. The topology, unlike the others in …

Body Biasing Techniques for Dynamic Comparators: A Systematic Survey

V Spinogatti, R Della Sala, C Bocciarelli, F Centurelli… - Electronics, 2024 - mdpi.com
Forward body biasing (FBB) has often been exploited in the literature for improving the
performance of both analog and digital building blocks. Recent works have explored the …

Fully Synthesizable Dynamic Voltage Comparator across technology nodes and scaled supply voltages

DH Bui, DM Tran, DD Caviglia… - 2024 IEEE International …, 2024 - ieeexplore.ieee.org
A fully synthesizable rail-to-rail dynamic voltage comparator referring to different technology
nodes and supply voltages down to 0.3 V is presented in this paper. The analyzed circuit is …

Reliability and Power Supply Scaling Effects on Nanoscale Comparators for Future Flash/SAR Analog to Digital Converter (ADC) Applications

NT Teja, K Karthikeya, J Ajayan - 2024 15th International …, 2024 - ieeexplore.ieee.org
The most of mixed-signal applications, including ADC and DLDO (digital low drop-out
regulators), depend on the dynamic comparators. Therefore, enhancing the performance & …

High-Performance Stacked Dynamic Comparator for Analog to Digital Converters

A Kannaujiya, V Sahu, AP Shah - 2024 28th International …, 2024 - ieeexplore.ieee.org
This work briefs the stacked dynamic comparator (SDC) for analog mixed-signal
applications. Four-clock switches make it work at high speed with reduced power. The input …

Design of a High-Precision Inverter-Based CMOS Comparator for High Accuracy Applications

AM Maghraby, I Bozyel… - 2024 IEEE 67th …, 2024 - ieeexplore.ieee.org
A new low-power, high-precision inverter-based CMOS comparator is introduced in this
paper. Inherent high-power consumption of CMOS inverter is controlled by a current-limiting …

Behavioral Analysis of Regenerative and Dynamic Comparators in Terms of Speed and Thermal Reliability in Low-Power Applications

K Karthikeya, NT Teja, N Satwika… - 2024 IEEE 9th …, 2024 - ieeexplore.ieee.org
Comparators are crucial parts of circuit design because they can compare two analog
voltage signals and provide a digital output based on this comparison. This study aims to …

Automated Design of a Strong-ARM Dynamic Comparator

J Jiang, Q Wu, Y Wang, Q Qin, J Hao… - … of Electronics Design …, 2024 - ieeexplore.ieee.org
This paper presents an automated design method for a Strong-ARM dynamic comparator.
The dynamic characteristics of the dynamic comparator are analyzed and fitted into static …

Two Novel 0.6 V,> 2 GHz Latched Comparators with Charge Pump-Based Dynamic Biasing

V Spinogatti, C Bocciarelli, R Della Sala… - Authorea …, 2024 - techrxiv.org
Charge pump-based (CPB) dynamic biasing can be exploited in latched comparators to
optimize the speed-noise tradeoff allowing operation at low supply voltage with high speed …

Design and Analysis of Different 2-Stage Dynamic Comparators for Low Power Consumption and High Speed

TV Sreelatha, SH Bharathi - 2024 IEEE International …, 2024 - ieeexplore.ieee.org
The proposed comparator architecture includes various kinds of comparators like dynamic
two-stage Conventional Comparator to compare with different designs like 19T Comparator …