Verifiable integrity guarantees for machine code programs
U Erlingsson, M Abadi, M Vrable - US Patent 8,104,021, 2012 - Google Patents
A verifier performs static checks of machine code to ensure that the code will execute safely.
After verification is performed, the code is executed. The code modules generated by the …
After verification is performed, the code is executed. The code modules generated by the …
Non-volatile memory with two phased programming
HY Tseng, D Dutta - US Patent 9,570,179, 2017 - Google Patents
Programming non-volatile memory includes applying a series of programming pulses to the
memory cells as part of a coarse/fine programming process. Between programming pulses …
memory cells as part of a coarse/fine programming process. Between programming pulses …
Automatic test generation for model-based code coverage
Z Kalmar, G Hamon, WJ Aldrich - US Patent 9,665,350, 2017 - Google Patents
A computer-implemented method includes obtaining a first representation of a system,
obtaining a set of test obligations, and automatically generating one or more test cases from …
obtaining a set of test obligations, and automatically generating one or more test cases from …
Model-based retiming with functional equivalence constraints
Y Gu, G Venkataramani - US Patent 9,779,195, 2017 - Google Patents
A system and method tests for functional equivalence prior to automatically retiming a high-
level specification. An Intermediate Representation (IR) includes one or more graphs or …
level specification. An Intermediate Representation (IR) includes one or more graphs or …
[PDF][PDF] Sign-off with Bounded Formal Verification Proofs
Formal property verification (also known as model checking) is a powerful methodology that
can be used to find corner-case bugs, improve verification efficiency and reduce the …
can be used to find corner-case bugs, improve verification efficiency and reduce the …
Probabilistic regression suites for functional verification
Methods, apparatus and systems are provided that enable the generation of random
regression Suites for verification of a hardware or software design to be formulated as …
regression Suites for verification of a hardware or software design to be formulated as …
Double lockout in non-volatile memory
HY Tseng, D Dutta - US Patent 9,875,805, 2018 - Google Patents
A double lockout programming technique is provided having a hidden delay between
programming and verification. A temporary lockout stage and a permanent lockout stage are …
programming and verification. A temporary lockout stage and a permanent lockout stage are …
Model-based retiming with functional equivalence constraints
Y Gu, G Venkataramani - US Patent 8,990,739, 2015 - Google Patents
BACKGROUND One goal of circuit design and/or program coding is to optimize some
aspect of a system with the goal of improving its quality. One Such optimization approach …
aspect of a system with the goal of improving its quality. One Such optimization approach …
Non-volatile memory with prior state sensing
D Dutta, HY Tseng, D Lee, K Oowada… - US Patent 9,548,130, 2017 - Google Patents
(57) ABSTRACT A non-volatile memory system comprises a plurality of memory cells
arranged in a three dimensional structure and one or more control circuits in communication …
arranged in a three dimensional structure and one or more control circuits in communication …
Method for mutation coverage during formal verification
P Goyal, A Jain - US Patent 8,990,746, 2015 - Google Patents
US8990746B1 - Method for mutation coverage during formal verification - Google Patents
US8990746B1 - Method for mutation coverage during formal verification - Google Patents …
US8990746B1 - Method for mutation coverage during formal verification - Google Patents …