[图书][B] Formal equivalence checking and design debugging

SY Huang, KTT Cheng - 2012 - books.google.com
Formal Equivalence Checking and Design Debugging covers two major topics in design
verification: logic equivalence checking and design debugging. The first part of the book …

[图书][B] Decision diagram techniques for micro-and nanoelectronic design handbook

SN Yanushkevich, DM Miller, VP Shmerko… - 2018 - taylorfrancis.com
Decision diagram (DD) techniques are very popular in the electronic design automation
(EDA) of integrated circuits, and for good reason. They can accurately simulate logic design …

[HTML][HTML] Efficient symbolic search for cost-optimal planning

Á Torralba, V Alcázar, P Kissmann, S Edelkamp - Artificial Intelligence, 2017 - Elsevier
In cost-optimal planning we aim to find a sequence of operators that achieve a set of goals
with minimum cost. Symbolic search with Binary Decision Diagrams (BDDs) performs …

[PDF][PDF] Binary decision diagrams

F Somenzi - NATO ASI SERIES F COMPUTER AND SYSTEMS …, 1999 - Citeseer
Binary Decision Diagrams Page 1 Binary Decision Diagrams Fabio SOMENZI Department
of Electrical and Computer Engineering University of Colorado at Boulder Abstract We …

Efficient manipulation of decision diagrams

F Somenzi - International Journal on Software Tools for Technology …, 2001 - Springer
Over the last decade significant progress has been made in the efficient implementation of
algorithms for the manipulation of decision diagrams. We review the main issues involved in …

[图书][B] The computer engineering handbook

VG Oklobdzija - 2001 - taylorfrancis.com
There is arguably no field in greater need of a comprehensive handbook than computer
engineering. The unparalleled rate of technological advancement, the explosion of …

Unbounded protocol compliance verification using interval property checking with invariants

MD Nguyen, M Thalmaier, M Wedler… - … on Computer-Aided …, 2008 - ieeexplore.ieee.org
We propose a methodology to formally prove protocol compliance for communication blocks
in System-on-Chip (SoC) designs. In this methodology, a set of operational properties is …

Property checking via structural analysis

J Baumgartner, A Kuehlmann, J Abraham - Computer Aided Verification …, 2002 - Springer
This paper describes a structurally-guided framework for the decomposition of a verification
task into subtasks, each solved by a specialized algorithm for overall efficiency. Our …

A history of satisfiability

J Franco, J Martin - Handbook of satisfiability, 2009 - ebooks.iospress.nl
This chapter traces the links between the notion of Satisfiability and the attempts by
mathematicians, philosophers, engineers, and scientists over the last 2300 years to develop …

Approximation and decomposition of binary decision diagrams

K Ravi, KL McMillan, TR Shiple… - Proceedings of the 35th …, 1998 - dl.acm.org
Efficient techniques for the manipulation of Binary Decision Diagrams (BDDs) are key to the
success of formal verification tools. Recent advances in reachability analysis and model …