High performance microprocessors require high levels of instruction supply. Branch
prediction has been the most important driver of this for nearly 30 years. Unfortunately …

Runahead execution improves processor performance by accurately prefetching long-
latency memory accesses. When a long-latency load causes the instruction window to fill up …

Graph structures are a natural representation of important and pervasive data. While graph
applications have significant parallelism, their characteristic pointer indirect loads to …

Cache prefetching is a traditional way to reduce memory access latency. In multi-core
systems, aggressive prefetching may harm the system. In the past, prefetching throttling …

Delinquent branches and loads remain key performance limiters in some applications. One
approach to mitigate them is pre-execution. Broadly, there are two classes of pre-execution …

Out-of-order cores rely on high-accuracy branch predictors to supply useful instructions to
the processor backend. However, there remains a large fraction of mispredictions caused by …

Single-thread performance improvement remains a central design goal for general purpose
processors. Microarchitectural designs for the core have reached a plateau over the past …

近期缓存预取算法的研究热点是使用基于模式识别的预测技术, 例如Lookahead,
推算访存请求的地址. 此类算法一方面很难学习访存行为中的依赖缓存失效 …

Graph structures naturally and efficiently capture relationships between entities, such as
individuals in a social network, pages in the World Wide Web, and amino acids in protein …

Delinquent branches (frequently mispredict) and loads (frequently miss) remain key IPC
bottlenecks in some applications. One approach to reduce their effect is pre-execution via …