FPGA-based prototyping of A 2D mesh/torus on-chip interconnect

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FPGA-based prototyping of A 2D mesh/torus on-chip interconnect

On Chip Network Routing for Tera-Scale Architectures

AS Vaidya, M Azimi, A Kumar - Routing Algorithms in Networks-on-Chip, 2014 - Springer

The emergence of Tera-scale architectures features the interconnection of tens to several
hundred general purpose cores to each other and with other IP blocks. The high level …

FPGA-based prototyping of A 2D mesh/torus on-chip interconnect

On Chip Network Routing for Tera-Scale Architectures

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