Advanced virtual prototyping for cyber-physical systems using RISC-V: implementation, verification and challenges

V Herdt, R Drechsler - Science China Information Sciences, 2022 - Springer
Virtual prototypes (VPs) are crucial in today's design flow. VPs are predominantly created in
SystemC transaction-level modeling (TLM) and are leveraged for early software …

Large circuit models: opportunities and challenges

L Chen, Y Chen, Z Chu, W Fang, TY Ho… - Science China …, 2024 - Springer
Within the electronic design automation (EDA) domain, artificial intelligence (AI)-driven
solutions have emerged as formidable tools, yet they typically augment rather than redefine …

[图书][B] Enhanced Virtual Prototyping

RDV Herdt, D Große, R Drechsler - 2021 - Springer
Virtual Prototypes (VPs) play a very important role to cope with the rising complexity in the
design flow of embedded devices. A VP is essentially an executable abstract model of the …

Embedding online runtime verification for fault disambiguation on robonaut2

B Kempa, P Zhang, PH Jones, J Zambreno… - … Conference on Formal …, 2020 - Springer
Abstract Robonaut2 (R2) is a humanoid robot onboard the International Space Station (ISS),
performing specialized tasks in collaboration with astronauts. After deployment, R2 …

The dawn of ai-native eda: Promises and challenges of large circuit models

L Chen, Y Chen, Z Chu, W Fang, TY Ho… - arXiv preprint arXiv …, 2024 - arxiv.org
Within the Electronic Design Automation (EDA) domain, AI-driven solutions have emerged
as formidable tools, yet they typically augment rather than redefine existing methodologies …

Formal security verification of concurrent firmware in SoCs using instruction-level abstraction for hardware

BY Huang, S Ray, A Gupta, JM Fung… - Proceedings of the 55th …, 2018 - dl.acm.org
Formal security verification of firmware interacting with hardware in modern Systems-on-
Chip (SoCs) is a critical research problem. This faces the following challenges:(1) design …

Early concolic testing of embedded binaries with virtual prototypes: A RISC-V case study

V Herdt, D Große, HM Le, R Drechsler - Proceedings of the 56th Annual …, 2019 - dl.acm.org
Extensive testing of IoT SW is very important to prevent errors and security vulnerabilities. In
the SW domain the automated concolic testing technique has been shown very effective. In …

Mesh based obfuscation of analog circuit properties

VV Rao, I Savidis - 2019 IEEE International Symposium on …, 2019 - ieeexplore.ieee.org
In this paper, a technique to design analog circuits with enhanced security is described. The
proposed key based obfuscation technique uses a mesh topology to obfuscate the physical …

Generating architecture-level abstractions from RTL designs for processors and accelerators part i: Determining architectural state variables

Y Zeng, BY Huang, H Zhang, A Gupta… - 2021 IEEE/ACM …, 2021 - ieeexplore.ieee.org
Today's Systems-on-Chips (SoCs) comprise general/special purpose programmable
processors and specialized hardware modules referred to as accelerators. These …

Formal verification of security critical hardware-firmware interactions in commercial SoCs

S Ray, N Ghosh, RJ Masti, A Kanuparthi… - Proceedings of the 56th …, 2019 - dl.acm.org
We present an effective methodology for formally verifying security-critical flows in a
commercial System-on-Chip (SoC) which involve extensive interaction between firmware …