Method for forming dielectric isolation region and Sige channels for CMOS integration of
nanosheet devices gen erally includes epitaxially growing a multilayer structure including …

5,061,644 5,079,616 5,091,333 5,091,767 5,093,699 5,098,850 5,105,247 5,108,947
5,156,995 5,159,413 5,164.359 5,166,767 5,223,043 5,236,546 5,238,869 5,256,594 …

(65) Prior Publication Data(Continued) US 2011 FOO49568 A1 Mar. 3, 2011 OTHER
PUBLICATIONS Related US Application Data 68 Applied Physics Letters 7, pp. 774-779 …

BACKGROUND Large Substrates with electronically active components distributed over the
extent of the substrate may be used in a variety of electronic systems, for example, in flat …

Semiconductor structures include a trench formed proximate a substrate including a first
semiconductor material. A crystalline material including a second semiconductor material …

US8173551B2 - Defect reduction using aspect ratio trapping - Google Patents
US8173551B2 - Defect reduction using aspect ratio trapping - Google Patents Defect …

5,091,333 5,091,767 5,093,699 5,098,850 5,105,247 5,108,947 5,156,995 5,159,413
5,164.359 5,166,767 5,223,043 5,236,546 5,238,869 5,256,594 5,269,852 5,269,876 …

US9153645B2 - Lattice-mismatched semiconductor structures with reduced dislocation
defect densities and related methods for device fabrication - Google Patents US9153645B2 …

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Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited
area regions having upper por tions Substantially exhausted of threading dislocations, as …