A review of the gate-all-around nanosheet FET process opportunities
S Mukesh, J Zhang - Electronics, 2022 - mdpi.com
In this paper, the innovations in device design of the gate-all-around (GAA) nanosheet FET
are reviewed. These innovations span enablement of multiple threshold voltages and …
are reviewed. These innovations span enablement of multiple threshold voltages and …
Germanium CMOS potential from material and process perspectives: Be more positive about germanium
A Toriumi, T Nishimura - Japanese Journal of Applied Physics, 2017 - iopscience.iop.org
CMOS miniaturization is now approaching the sub-10 nm level, and further downscaling is
expected. This size scaling will end sooner or later, however, because the typical size is …
expected. This size scaling will end sooner or later, however, because the typical size is …
Ballistic two-dimensional InSe transistors
Abstract The International Roadmap for Devices and Systems (IRDS) forecasts that, for
silicon-based metal–oxide–semiconductor (MOS) field-effect transistors (FETs), the scaling …
silicon-based metal–oxide–semiconductor (MOS) field-effect transistors (FETs), the scaling …
Mobility Enhancement of Strained MoS2 Transistor on Flat Substrate
Strain engineering has been proposed as a promising method to boost the carrier mobility of
two-dimensional (2D) semiconductors. However, state-of-the-art straining approaches are …
two-dimensional (2D) semiconductors. However, state-of-the-art straining approaches are …
Challenges and limitations of CMOS scaling for FinFET and beyond architectures
A Razavieh, P Zeitzoff, EJ Nowak - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
Scaling trends of FinFET architecture, with focus on Front-End-of-Line (FEOL), and Middle-of-
Line (MOL) device parameters, is systematically investigated. It is concluded that the …
Line (MOL) device parameters, is systematically investigated. It is concluded that the …
Carbon nanotube transistors scaled to a 40-nanometer footprint
The International Technology Roadmap for Semiconductors challenges the device research
community to reduce the transistor footprint containing all components to 40 nanometers …
community to reduce the transistor footprint containing all components to 40 nanometers …
Nanowire & nanosheet FETs for ultra-scaled, high-density logic and memory applications
A Veloso, T Huynh-Bao, P Matagne, D Jang… - Solid-State …, 2020 - Elsevier
We report on vertically stacked lateral nanowires (NW)/nanosheets (NS) gate-all-around
(GAA) FET devices as promising candidates to obtain a better power-performance metric for …
(GAA) FET devices as promising candidates to obtain a better power-performance metric for …
Directed self-assembly of block copolymers for 7 nanometre FinFET technology and beyond
The drive to deliver increasingly powerful and feature-rich integrated circuits has made
technology node scaling—the process of reducing transistor dimensions and increasing …
technology node scaling—the process of reducing transistor dimensions and increasing …
Scaling challenges for advanced CMOS devices
The economic health of the semiconductor industry requires substantial scaling of chip
power, performance, and area with every new technology node that is ramped into …
power, performance, and area with every new technology node that is ramped into …
Exploring the performance of 3-D nanosheet FET in inversion and junctionless modes: Device and circuit-level analysis and comparison
In this article, the performance of 3-D nanosheet FET (NS-FET) in inversion (INV) and
junctionless (JL) modes is demonstrated and compared at both device and circuit levels. In …
junctionless (JL) modes is demonstrated and compared at both device and circuit levels. In …