Towards automatic high-level code deployment on reconfigurable platforms: A survey of high-level synthesis tools and toolchains

MW Numan, BJ Phillips, GS Puddy, K Falkner - IEEE Access, 2020 - ieeexplore.ieee.org
Heterogeneous computing systems with tightly coupled processors and reconfigurable logic
blocks provide great scope to improve software performance by executing each section of …

Using HW/SW codesign for deep neural network hardware accelerator targeting low-resources embedded processors

E Manor, S Greenberg - IEEE Access, 2022 - ieeexplore.ieee.org
The usage of RISC-based embedded processors, aimed at low cost and low power, is
becoming an increasingly popular ecosystem for both hardware and software development …

Implications of reduced-precision computations in HPC: Performance, energy and error

S Cherubin, G Agosta, I Lasri, E Rohou… - Parallel computing is …, 2018 - ebooks.iospress.nl
Error-tolerating applications are increasingly common in the emerging field of real-time
HPC. Proposals have been made at the hardware level to take advantage of inherent …

Embedded operating system optimization through floating to fixed point compiler transformation

D Cattaneo, A Di Bello, S Cherubin… - 2018 21st Euromicro …, 2018 - ieeexplore.ieee.org
Architectures targeted at embedded systems often have limited floating point computation
capabilities, and in many cases do not provide any hardware support. In this work, we …

Flight simulator-based verification for model-based avionics applications on multi-core targets

P Ulbig, D Müller, C Torens, CC Insaurralde… - AIAA Scitech 2019 …, 2019 - arc.aiaa.org
Technological advances in Cyber-Physical Systems (CPS) trigger the growth of the cyber
layer in aircraft. They come with the demand for higher throughput and computational power …

Bridging high-level synthesis and application-specific arithmetic: The case study of floating-point summations

Y Uguen, F de Dinechin… - 2017 27th International …, 2017 - ieeexplore.ieee.org
FPGAs are well known for their ability to perform non-standard computations not supported
by classical microprocessors. Many libraries of highly customizable application-specific IPs …

Wcet-aware parallelization of model-based applications for multi-cores: The argo approach

S Derrien, I Puaut, P Alefragis… - … , Automation & Test …, 2017 - ieeexplore.ieee.org
Parallel architectures are nowadays not only confined to the domain of high performance
computing, they are also increasingly used in embedded time-critical systems. The ARGO …

Modeling and simulation based development of an enhanced ground proximity warning system for multicore targets

U Durak, D Müller, F Möcke, CB Koch - Proceedings of the Model-driven …, 2018 - dl.acm.org
The advances in Cyber-Physical Systems (CPS) are also effecting the aeronautics. The
growth of the cyber layer in aircraft is demanding higher throughput and eventually multi …

Application-specific arithmetic in high-level synthesis tools

Y Uguen, FD Dinechin, V Lezaud… - ACM Transactions on …, 2020 - dl.acm.org
This work studies hardware-specific optimization opportunities currently unexploited by high-
level synthesis compilers. Some of these optimizations are specializations of floating-point …

Communication-based power modelling for heterogeneous multiprocessor architectures

B Roux, M Gautier, O Sentieys… - 2016 IEEE 10th …, 2016 - ieeexplore.ieee.org
Programming heterogeneous multiprocessor architectures is a real challenge dealing with a
huge design space. Computer-aided design and development tools try to circumvent this …