This paper presents an adaptive finite impulse response (FIR) equalizer with continuous-
time wide-bandwidth delay line in CMOS 0.25-mum process for 2.5-Gb/s to 3.5-Gb/s data …

A novel approach to equalization of high-speed serial links combines both amplitude pre-
emphasis to correct for intersymbol interference and phase pre-emphasis to compensate for …

This paper presents a 40 Gb/s serial-link receiver including an adaptive equalizer and a
CDR circuit. A parallel-path equalizing filter is used to compensate the high-frequency loss …

A single-lane, dual-channel, 5-Gb/s serial link redriver with no clock data recovery (CDR) or
phase-locked loop (PLL) has been developed by using a standard 0.13-μm CMOS …

This brief presents a 5-Gb/s adaptive equalizer that compensates for the PCI Express
channel loss of 14 dB at 2.5 GHz. This equalizing filter uses low-voltage zero generators …

This paper presents a four channel receiver for high-speed signal conditioning. Each
channel consists of a continuous time linear equalizer (CTLE) and a dual loop CDR with …

This paper presents a continuous-time equalizer which provides a low-power, small area
and low-cost solution for a DDI implementation. Proposed equalizer adopts clock …

A new dual-loop adaptive continuous-time linear equalizer (CTLE) based on power
comparison is proposed to realize a 25-Gb/s optical transmitter. The adaptive CTLE controls …

This paper presents a very robust 6x OSR receiver for 0.2–2 Gb/s binary NRZ signals,
introducing an adaptive equalizer that is auto-calibrating on sample data statistics for …

This paper presents a fully integrated imaging receiver for high data rate wireless optical
communication. A 3× 3 matrix of Spatially Modulated Light detectors (SML), each with 730 …