Given the need for efficient high-performance computing, computer architectures combining
central processing units (CPUs), graphics processing units (GPUs), and field-programmable …

When a computational task tolerates a relaxation of its specification or when an algorithm
tolerates the effects of noise in its execution, hardware, system software, and programming …

With each new technology generation, the available resources on Field Programmable Gate
Arrays increase, making them more attractive for partial access from multiple users. They get …

In this paper, we present the first automated system-level analysis of multicore CPUs based
on ARMv8 64-bit architecture (8-core, 28nm X-Gene 2 micro-server by AppliedMicro) when …

This book is an introduction to the design of asynchronous circuits. It is an updated and
significantly extended version of an eight-chapter tutorial that first appeared as Part I in the …

Many emerging applications such as the internet of things, wearables, and sensor networks
have ultra-low-power requirements. At the same time, cost and programmability …

The performance of an IC degrades over its lifetime, ultimately resulting in IC failure. In this
article, we present a hardware attack (called MAGIC) to maliciously accelerate NBTI aging …

Timing errors that are caused by the timing violations of sensitized circuit paths, have
emerged as an important threat to the reliability of synchronous digital circuits. To protect …

With the end of conventional CMOS scaling, efficient resiliency solutions are needed to
address the increased likelihood of hardware errors. Silent data corruptions (SDCs) are …

Modern CPUs dynamically scale voltage and frequency for efficiency. However, too low
voltages can result in security-critical errors. Hence, vendors use a generous safety margin …