We propose a lightweight scheme where the formation of a data block is changed in such a
way that it can tolerate soft errors significantly better than the baseline. The key insight …

Spin-transfer torque magnetic random access memory (STT-MRAM) is a promising cache
memory candidate due to its high density, low leakage power, and nonvolatility. Multilevel …

Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a promising
emerging memory technology for on-chip caches. It has a low read access time and low …

Static random access memory–(SRAM) based field programmable gate arrays (FPGAs) are
currently facing challenges of limited capacity and high leakage power. To solve this …

Compression techniques at the last-level cache and the DRAM play an important role in
improving system performance by increasing their effective capacities. A compressed block …

Multi Level Cell (MLC) Spin Transfer Torque RAM (STT-RAM) provides higher density than
Single Level Cell (SLC) STT-RAM by storing two digital bits in a single cell, and is proposed …

Spin-transfer torque RAM (STT-RAM) is a future technology for ON-chip caches. However, it
suffers from high read and write error rates. Concurrently dealing with these errors is quite …

Spin-transfer torque RAM (STT-RAM) is an emerging non-volatile memory that has been
recognized as the potential candidate to replace SRAM. Compared with SRAM, STT-RAM …

Traditional memory technologies face severe challenges in meeting the ever-increasing
power and memory bandwidth requirements for high-performance computing and big-data …

In this paper, we present a novel cache design based on Multi-Level Cell Spin-Transfer
Torque RAM (MLC STT-RAM) that can dynamically adjust the set capacity and associativity …