Cache memory: an analysis on performance issues

A Alsharef, P Jain, M Arora, SR Zahra… - 2021 8th international …, 2021 - ieeexplore.ieee.org
Cache memory is mainly inculcated in systems to overcome the gap created in-between the
main memory and CPUs due to their performance issues. Since, the speed of the processors …

Critical analysis of cache memory performance concerning miss rate and power consumption

HV Dave, NA Kotak - International Journal of Embedded …, 2022 - inderscienceonline.com
There has been constant growth in the usage of mobile devices in the last decade. As
necessary demand by the technological marketplace, mobile devices are designed per the …

Design and Performance Analysis of a Fast 4-Way Set Associative Cache Controller using Tree Pseudo Least Recently Used Algorithm

MAAZ Hazlan, TS Gunawan… - … Journal of Electrical …, 2023 - section.iaesonline.com
In the realm of modern computing, cache memory serves as an essential intermediary,
mitigating the speed disparity between rapid processors and slower main memory. Central …

Enhancement of cache memory performance

I Lokegaonkar, D Nair, V Kulkarni - 2021 3rd International …, 2021 - ieeexplore.ieee.org
Cache memory is small, high-speed buffer memory that lies in between the CPU and the
primary unit. Optimization and enhancement of cache memory is a continuously growing …

A Proposed CPU Job-Scheduling Technique Based on Round Robin Method Using Dual Synchronized Time-Slices

SA Hussein, EIA Kareem - Ingenierie des Systemes d' …, 2024 - search.proquest.com
A major aspect of distributed systems is task scheduling. How significant is it to adequately
allocate tasks to each one of the computer's processors for the purpose of achieving better …

Design of Reconfigurable Cache Memory Using Verilog HDL

KN Manjunatha, SS Yellampalli - … Conference on Electrical …, 2018 - ieeexplore.ieee.org
Verilog Hardware Description Language is used to design cache memory which involves
direct mapping and set associative cache. Further set associative cache involves two-way …

Cache Computing for Dew Devices at the Edge Networks

F Adhikary, SK Paul, MS Obaidat, D De… - Dew Computing: The …, 2023 - Springer
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Evaluation of cache-based memory hierarchy for HEVC video decoding

G de Souza, S Bampi, A Cerveira… - … 33rd Symposium on …, 2020 - ieeexplore.ieee.org
The intra-frame and inter-frame prediction techniques for video encoding, although not
exclusively, are key factors in the architectural design of many codec specifications. Adding …

Minimizing the Cache Memory Miss Ratio Using Modified Replacement Algorithm (MCAR).

SA Hussein, MR Kareem… - Ingénierie des Systèmes …, 2024 - search.ebscohost.com
Caching is a key method used to close the latency gap between memory and the CPU by
using locality in memory accesses. varied cache replacement algorithms have radically …

Storage memory/NVM based executable memory interface IP for advanced IoT applications

MK Dinesh, R Bhakthavatchalu - 2016 international conference …, 2016 - ieeexplore.ieee.org
Internet of Things (IoT) devices is getting increasingly popular in every aspect of life. From
health care monitors, activity/sleep trackers to industry/home automation, IoT devices and …