A survey on fault injection methods of digital integrated circuits

M Eslami, B Ghavami, M Raji, A Mahani - Integration, 2020 - Elsevier
One of the most popular methods for reliability assessment of digital circuits is Fault Injection
(FI) in which the behavior of the circuit is simulated in presence of faults. In this paper, we …

Solving the third-shift problem in IC piracy with test-aware logic locking

SM Plaza, IL Markov - … on Computer-Aided Design of Integrated …, 2015 - ieeexplore.ieee.org
The increasing IC manufacturing cost encourages a business model where design houses
outsource IC fabrication to remote foundries. Despite cost savings, this model exposes …

A stochastic computational approach for accurate and efficient reliability evaluation

J Han, H Chen, J Liang, P Zhu, Z Yang… - IEEE Transactions on …, 2012 - ieeexplore.ieee.org
Reliability is fast becoming a major concern due to the nanometric scaling of CMOS
technology. Accurate analytical approaches for the reliability evaluation of logic circuits …

Gate‐Level Circuit Reliability Analysis: A Survey

R Xiao, C Chen - VLSI Design, 2014 - Wiley Online Library
Circuit reliability has become a growing concern in today's nanoelectronics, which motivates
strong research interest over the years in reliability analysis and reliability‐oriented circuit …

Efficient algorithms to accurately compute derating factors of digital circuits

H Asadi, MB Tahoori, M Fazeli, SG Miremadi - Microelectronics Reliability, 2012 - Elsevier
Fast, accurate, and detailed Soft Error Rate (SER) estimation of digital circuits is essential for
cost-efficient reliable design. A major step to accurately estimate a circuit SER is the …

Layout-based soft error rate estimation framework considering multiple transient faults—From device to circuit level

HM Huang, CHP Wen - … Aided Design of Integrated Circuits and …, 2015 - ieeexplore.ieee.org
This paper investigated the soft errors caused by particle strikes, such as high-energy
neutrons, extending beyond the deep submicrometer era. Considering the structure of the …

Robust discrete synthesis against unspecified disturbances

R Majumdar, E Render, P Tabuada - Proceedings of the 14th …, 2011 - dl.acm.org
Systems working in uncertain environments should possess a robustness property, which
ensures that the behaviours of the system remain close to the original behaviours under the …

Characterization of logical masking and error propagation in combinational circuits and effects on system vulnerability

N George, J Lach - … IEEE/IFIP 41st International Conference on …, 2011 - ieeexplore.ieee.org
Among the masking phenomena that render immunity to combinational logic circuits from
soft errors, logical masking is the hardest to model and characterize. This is mainly attributed …

MASkIt: Soft error rate estimation for combinational circuits

M Anglada, R Canal, JL Aragón… - 2016 IEEE 34th …, 2016 - ieeexplore.ieee.org
Integrated circuits are getting increasingly vulnerable to soft errors; as a consequence, soft
error rate (SER) estimation has become an important and very challenging goal. In this work …

A low-cost, systematic methodology for soft error robustness of logic circuits

KC Wu, D Marculescu - IEEE transactions on very large scale …, 2012 - ieeexplore.ieee.org
Due to current technology scaling trends such as shrinking feature sizes and decreasing
supply voltages, circuit reliability is becoming more susceptible to radiation-induced …