Selective gray-coded bit-plane based low-complexity motion estimation and its hardware architecture
Today, many consumer electronics devices have video capturing capability which is one of
the most time, power and memory consuming application. Motion estimation (ME) is the key …
the most time, power and memory consuming application. Motion estimation (ME) is the key …
Bit plane matching based variable block size motion estimation method and its hardware architecture
Variable Block Size Motion Estimation (VBSME) is one of the most important features of state-
of-theart video encoders. In the H. 264/AVC encoder, the computational complexity of …
of-theart video encoders. In the H. 264/AVC encoder, the computational complexity of …
Low power VLSI architectures for one bit transformation based fast motion estimation
SK Chatterjee, I Chakrabarti - IEEE Transactions on Consumer …, 2010 - ieeexplore.ieee.org
In the present paper, architectures implementing fixed block size and variable block size
(VBS) motion estimation (ME) algorithms on one bit transformed (1-BT) image frames have …
(VBS) motion estimation (ME) algorithms on one bit transformed (1-BT) image frames have …
High performance hardware architectures for one bit transform based single and multiple reference frame motion estimation
Motion Estimation (ME) is the most computationally intensive part of video compression and
video enhancement systems. One bit transform (1BT) based ME algorithms have low …
video enhancement systems. One bit transform (1BT) based ME algorithms have low …
Constrained one-bit transform based fast block motion estimation using adaptive search range
O Urhan - IEEE Transactions on Consumer Electronics, 2010 - ieeexplore.ieee.org
An efficient adaptive search range determination approach for constrained one-bit transform
based block motion estimation is presented in this paper. This approach employs only one …
based block motion estimation is presented in this paper. This approach employs only one …
Power efficient motion estimation algorithm and architecture based on pixel truncation
SK Chatterjee, I Chakrabarti - IEEE Transactions on Consumer …, 2011 - ieeexplore.ieee.org
A new block matching algorithm and its VLSI architecture for performing Motion Estimation
(ME) are presented in this paper. In the reported fast two stage search algorithm, ME is …
(ME) are presented in this paper. In the reported fast two stage search algorithm, ME is …
FPGA architecture of the LDPS Motion Estimation for H. 264/AVC Video Coding
Motion estimation is a highly computational demanding operation during video compression
process and significantly affects the output quality of an encoded sequence. Special …
process and significantly affects the output quality of an encoded sequence. Special …
A low energy adaptive hardware for H. 264 multiple reference frame motion estimation
Multiple reference frame motion estimation (MRF ME) increases the video coding efficiency
at the expense of increased computational complexity and energy consumption. Therefore …
at the expense of increased computational complexity and energy consumption. Therefore …
High performance hardware architecture for constrained one-bit transform based motion estimation
Motion estimation (ME) processes is considered as the most computationally intensive part
of the conventional video compression standards. Low bit-depth representation based ME …
of the conventional video compression standards. Low bit-depth representation based ME …
[PDF][PDF] 高性能并行比特变换运动估计硬件架构设计
陈运必， 郭立， 李正东， 池凌鸿 - 电子与信息学报, 2011 - edit.jeit.ac.cn
为了满足便携式实时全高清视频的处理要求, 该文基于1 维源像素线性阵列,
提出一种新的多宏块并行比特变换运动估计结构, 克服以往2 维阵列消耗资源较多且延时大的 …
提出一种新的多宏块并行比特变换运动估计结构, 克服以往2 维阵列消耗资源较多且延时大的 …