Vertical GAAFETs for the ultimate CMOS scaling

D Yakimets, G Eneman, P Schuddinck… - … on Electron Devices, 2015 - ieeexplore.ieee.org
In this paper, we compare the performances of FinFETs, lateral gate-all-around (GAA) FETs,
and vertical GAAFETs (VFETs) at 7-nm node dimensions and beyond. Comparison is done …

The Wigner Monte Carlo method for nanoelectronic devices

D Querlioz, P Dollfus, M Mouis - ISTE Wiley: London, UK, 2010 - Wiley Online Library
For many years, the semi-classical Boltzmann approach to transport in semiconductors has
been very successful in interpreting the physics of electron devices, in a fast evolving …

Device and circuit exploration of multi-nanosheet transistor for sub-3 nm technology node

Y Seon, J Chang, C Yoo, J Jeon - Electronics, 2021 - mdpi.com
A multi-nanosheet field-effect transistor (mNS-FET) device was developed to maximize gate
controllability while making the channel in the form of a sheet. The mNS-FET has superior …

Size dependence of surface-roughness-limited mobility in silicon-nanowire FETs

S Poli, MG Pala, T Poiroux… - … on Electron Devices, 2008 - ieeexplore.ieee.org
Lateral size effects on surface-roughness-limited mobility in silicon-nanowire FETs are
analyzed by means of a full-quantum 3-D self-consistent simulation. A statistical analysis is …

Analysis of carrier transport in short-channel MOSFETs

A Majumdar, DA Antoniadis - IEEE Transactions on Electron …, 2014 - ieeexplore.ieee.org
A method for extracting transport parameters in short-channel FETs is presented in the
context of the Lundstrom model for quasi-ballistic short-channel FETs. The parameters …

Extraction of mobility from quantum transport calculations of type-ii superlattices

J Glennon, F Bertazzi, A Tibaldi, E Bellotti - Physical Review Applied, 2023 - APS
Type-II superlattices (T2SLs) are being investigated as an alternative to traditional bulk
materials in infrared photodetectors due to predicted fundamental advantages. Subject to …

Design and simulation of steep-slope silicon cold source FETs with effective carrier distribution model

W Gan, RJ Prentki, F Liu, J Bu, K Luo… - … on Electron Devices, 2020 - ieeexplore.ieee.org
The cold source field-effect transistor (CSFET), enabled by novel source engineering, is a
promising alternative to achieve sub-60 mV/dec steep-slope switching. For the first time, we …

Variability in Si nanowire MOSFETs due to the combined effect of interface roughness and random dopants: A fully three-dimensional NEGF simulation study

A Martinez, N Seoane, AR Brown… - … on electron devices, 2010 - ieeexplore.ieee.org
In this paper, we study the impact of surface roughness and its combination with random
discrete dopants on the current variability in nanometer-scale nanowire metal …

On backscattering and mobility in nanoscale silicon MOSFETs

C Jeong, DA Antoniadis… - IEEE Transactions on …, 2009 - ieeexplore.ieee.org
The DC current-voltage characteristics of an n-channel silicon MOSFET with an effective
gate length of about 60 nm are analyzed and interpreted in terms of scattering theory. The …

Three-dimensional real-space simulation of surface roughness in silicon nanowire FETs

C Buran, MG Pala, M Bescond… - IEEE Transactions on …, 2009 - ieeexplore.ieee.org
We address the transport properties of narrow gate-all-around silicon nanowires in the
presence of surface-roughness (SR) scattering at the Si/SiO 2 interface, considering …