Analog Integrated Circuit Routing Techniques: An Extensive Review

RMF Martins, NCC Lourenço - IEEE Access, 2023 - ieeexplore.ieee.org
Routing techniques for analog and radio-frequency (A/RF) integrated circuit (IC) design
automation have been proposed in the literature for over three decades. On those, an …

AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation

N Lourenço, R Martins, A Canelas, R Povoa, N Horta - Integration, 2016 - Elsevier
This paper presents AIDA, an analog integrated circuit design automation environment,
which implements a design flow from a circuit-level specification to physical layout …

Two-step RF IC block synthesis with preoptimized inductors and full layout generation in-the-loop

R Martins, N Lourenço, F Passos… - … on Computer-Aided …, 2018 - ieeexplore.ieee.org
In this paper, an analysis of the methodologies proposed in the past years to automate the
synthesis of radio-frequency (RF) integrated circuit blocks is presented. In the light of this …

A mixed domain sizing approach for RF circuit synthesis

E Afacan, G Dündar - … on Design and Diagnostics of Electronic …, 2016 - ieeexplore.ieee.org
This study presents a parasitic-aware RF circuit synthesis tool, in which layout-induced
parasitics of passive devices are captured by using sophisticated equivalent models for …

Design-Aware Parasitic-Aware Simulation Based Automation and Optimization of Highly Linear RF CMOS Power Amplifiers

RA Onsy, M El-Nozahi, H Ragai - Electronics, 2023 - mdpi.com
In this paper, a parasitic-design-aware simulation-based design tool is proposed for highly
linear RF power amplifiers. The main aim of the proposed tool is to speed up the design …

Stochastic-based placement template generator for analog IC layout-aware synthesis

R Martins, N Lourenco, A Canelas, N Horta - Integration, 2017 - Elsevier
In this paper, a methodology for automatic generation of placement templates for analog
integrated circuit design targeted to state-of-the-art optimization-based layout-aware circuit …

PV-aware analog sizing for robust analog layout retargeting with optical proximity correction

X Dong, L Zhang - ACM Transactions on Design Automation of …, 2018 - dl.acm.org
For analog integrated circuits (ICs) in nanometer technology nodes, process variation (PV)
induced by lithography may not only cause serious wafer pattern distortion, but also result in …

On-the-fly exploration of placement templates for analog IC layout-aware sizing methodologies

R Martins, A Canelas, N Lourenço… - 2016 13th International …, 2016 - ieeexplore.ieee.org
In this paper, a methodology for automatic generation of placement templates for analog
integrated circuit (IC) design is proposed and targeted to state-of-the-art layout-aware circuit …

Placement and routing method for analogue layout generation using modified cuckoo optimisation algorithm

SM Anisheh, H Shamsi - IET Circuits, Devices & Systems, 2018 - Wiley Online Library
This study presents a new placement and routing method for analogue integrated circuit
layout generation based on an evolutionary algorithm, which is called modified cuckoo …

Analog circuits sizing using multi-objective evo-lutionary algorithm based on decomposition

M Nohtanipour, MH Maghami… - Informacije MIDEM, 2021 - ojs.midem-drustvo.si
Several analog circuit design has been suggested where a layout generator is used after a
circuit sizing. But, many iterations between circuit sizing and layout generator stages are …